fixing violations in backend

[asicengineer1]

Hi all,
i'm a front end designer, who is interested in knowing the P&R flow. i know it consists of floorplanning, placement, cts and routing mostly. but, i'm not sure at what point of time, setup and hold violations are fixed. for instance, i came to know that setup are fixed before cts itself and hold after routing is done.

i don't know if i'm right about this also, could someone help me out with this ? i'd like to know when the violations are getting fixed and the reason behind why that particular stage is chosen to fix them.

Thanks.

 

[srkumar81]

you are right. setup is fixed before cts i.e., in placement stage where clock path is ideal. thats y we cannot fix hold. but hold is fixed after cts but before routing. after routing we cannot insert hold buffers.

 

[darylz]

Can setup only be fixed by placement and front-end?

 

[skymusic]

Now, some P&R tools can use clock skew to fix setup time violation. And some times, after cks, new setup time violations maybe occur. So, setup time violation should be re-fixed, after cks. But only few case, fix setup violation after routing.

 

[millsjam]

Just as an interesting side note - individual block builders may see fails on input-to-flop paths and flop-to-output paths of their blocks because of the constraints that have been applied to the block. The block builder would then need to check to ensure that the timing constraints on these paths are correct. Early on in a chip build the timing constraints may be overly pessimistic (to be on the safe side). As the TA results for the block builds in the chip become available then the constraints should be updated. So what an individual block builder may see as a failure on their input and output paths could be fixed without having to do any more placement and routing.