Taher_Selim
Member level 5
Hello,
I had to use fixed_package in VHDL. In synthesis, alot of logic produced in my circuit. I have read in user guide of fixed_package that some generics can be changed in order to optimize the logic. it is mentioned typically that we can use the following as a package:
I created this package in separate file. In my design file I used "use work.my_opt_fixed.all;" instead of "use ieee.fixed_pkg.all;"
My problem is that synthesis tool (precision) can't recognize my_opt_fixed , it gives an error.
Do u have an idea how to control these generics?
I will be grateful also if you give me some hints about optimizing synthesis logic for fixed point operations.
Thanks in advance,
I had to use fixed_package in VHDL. In synthesis, alot of logic produced in my circuit. I have read in user guide of fixed_package that some generics can be changed in order to optimize the logic. it is mentioned typically that we can use the following as a package:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 package my_opt_fixed is new ieee.fixed_generic_pkg generic map ( -- Truncate, don't round fixed_round_style => IEEE.fixed_float_types.fixed_truncate, -- wrap, don't saturate fixed_overflow_style => IEEE.fixed_float_types.fixed_wrap, fixed_guard_bits => 0, -- Don't need the extra guard bits no_warning => true -- turn warnings off );
I created this package in separate file. In my design file I used "use work.my_opt_fixed.all;" instead of "use ieee.fixed_pkg.all;"
My problem is that synthesis tool (precision) can't recognize my_opt_fixed , it gives an error.
Do u have an idea how to control these generics?
I will be grateful also if you give me some hints about optimizing synthesis logic for fixed point operations.
Thanks in advance,
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