fixed-point signed multiplication

[siva_7517]

verilog signed multiplier fixed-point

Hi,

I am currently doing a FFT for 8 point. Basically, I
have problem in fixed-point multiplication because
there is a extended sign bit before the adding. I have
no idea on how to write this in verilog code.

I try with this verilog code :

assign A = B*C

but it giving a wrong answer.


the example of calculation is shown below:



-----------------1.110 ____________ -0.25 B
--------------x 0.110 ____________ 0.75 C
-----------------------
---------------- 0000
------------111110------------------->extended sign bit
------------11110--------------------->extended sign bit
----------+0000
-----------------------------
----------11110100 _______________-0.1875 A



When we do a fixed point multiplication there is extra sign bit in inserted before the adding is done. I have difficulty on how to intepret this in verilog.thanx

Siva

 

[steven852]

verilog codings for fixed point multiplication

An example of sign extension:

input [7:0] a, b;

reg [8:0] signed_a, signed_b;

always (.. something ..) begin
signed_a = {a[7], a};
signed_b = {b[7], b};
.. something else
end

 

[siva_7517]

signed fix point

Hi,

Thanx for the guide. I am a bit confused in the coding on concatenation operator that have been used. Can I have explanation on that?
Thanks in advance

Siva

 

[steven852]

The concatenate operator combines the MSB of a (and b) with a to form an 9-bit value. For example

a = 8'b1000_0111;

{a[7],a} = 9'b1_1000_0111;