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fixed point representation

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lokesh@88

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sir
i want to design one model where input and output both are fixed point . if we will give some selected input then output should be its corresponding output. i have written a code is it write?



Code VHDL - [expand]
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library IEEE_proposed;
use IEEE_proposed.fixed_pkg.ALL;
entity inv_q is
 
  port ( address : in ufixed(1 downto -2);
         data : out ufixed(1 downto -8) );
end inv_q;
 
architecture Behavioral of inv_q is
 
begin
 
process (address)
   begin
     case address is
       when "0000" => data <= "1000001101";
       when "0001" => data <= "1001010011";
       when "0010" => data <= "0111100001";
       when "0011" => data <= "0111000000";
       when "0100" => data <= "0110100101";
       when "0101" => data <= "0110001110";
       when "0110" => data <= "0101111001";
       when "0111" => data <= "0101100111";
       when "1001" => data <= "0101010111";
       when "1010" => data <= "0101001000";
        when others => data <="0000000000";
     end case;
  end process;
 
end Behavioral;

 
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FvM

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The code is basically correct and synthesizable, as far as I'm aware of. I would use to_ufixed() for a visual representation of literals.

If the look-up table is intended for synthesis in internal block RAM, it may need registered addresses, depending on the used FPGA family.
 

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