fixed point multiplication

[siva_7517]

Hi,



-----------------1.110 ____________ -0.25 B
--------------X 0.110 ____________ 0.75 C
-------------------------
---------------- 0000
------------111110------------------->extended sign bit
------------11110--------------------->extended sign bit
----------+0000
-----------------------------
----------11110100 _______________-0.1875 A



i understand with concept of increase the output bit........but when we do a fixed point multiplication there is extra sign bit in inserted before the adding is done. I have difficulty on how to intepret this in verilog.thanx

 

[Circuit_seller]

Hi

you should shift it one bit to left.