Fixed point multiplication in Verilog

[krishvamsi]

i have two 8 bit signed numbers which i'd represented in fixed-point . one is -3.15 = 1100.1110 , other number is 5.1 = 0101.0010 . now i want to obtain the product of these two numbers in verilog. Manually i got the product as 0100000111111100 which is not equal to -16.065. how should i make it equal to manual result ?

 

[FvM]

What's the intended result format? You are apparently using signed 4.4 format, the "manual multiply" result isn't correct for signed multiply.

 

[krishvamsi]

the intended result should be in 16 bit signed fixed-point format which should be equivalent to that actual product i.e -16.065

 

[FvM]

should be in 16 bit signed fixed-point format

16 bit what? 8.8?

I get 11101111 11111100 in signed multiply.

 

[asdf44]

I see -50*82=-4100

Shift 8 for the 4+4 fractional bits:

-4100/2^8 = 16.0156

Looks correct with a little rounding error

 

[krishvamsi]

16 bit what? 8.8?

I get 11101111 11111100 in signed multiply.

yes exactly . can u tell me the logic u used ? i'll be using it in verilog

- - - Updated - - -

I see -50*82=-4100

Shift 8 for the 4+4 fractional bits:

-4100/2^8 = 16.0156

Looks correct with a little rounding error

can u please elaborate this ? i have 5.1 and -3.15 . from where u got -50 and 82 ?

 

[asdf44]

From the binary values in your own post

11001110 is -50
01010010 is 82

That's what the values are to the verilog code (if declared as signed).

wire signed [7:0] a = 8'b11001110;
wire signed [7:0] b = 8'b01010010;

wire signed [15:0] c = a*b;

C is 11101111 11111100 or -4100 in signed decimal