Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Fixed Point division in VHDL

Status
Not open for further replies.

info_req

Member level 5
Joined
Jun 20, 2007
Messages
81
Helped
6
Reputation
12
Reaction score
4
Trophy points
1,288
Location
Pakistan
Activity points
1,764
Hello dear,
I need algoritm/ guideline on fiexed point division in vhdl.
Secodnly, how to check that in how many cycles FPGA performs an operation(i.e. +, -, / etc.).
 

ddt694

Full Member level 3
Joined
Dec 12, 2002
Messages
170
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,296
Activity points
1,400
'paper and pencil' method is easy to design
you can google it
 

    info_req

    Points: 2
    Helpful Answer Positive Rating

ddboy40

Member level 3
Joined
Nov 26, 2006
Messages
62
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,724
info_req said:
Hello dear,
I need algoritm/ guideline on fiexed point division in vhdl.
Secodnly, how to check that in how many cycles FPGA performs an operation(i.e. +, -, / etc.).

we al know the pensil and paper method. Can someone explain to us/me how to check the number of cycles an algorithm needs ?
thanks in advance.
 

vfdff

Newbie level 4
Joined
Jun 26, 2007
Messages
5
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,281
Activity points
1,323
can't be used lmp in stand ??
 

rrrrr12345

Member level 1
Joined
May 5, 2007
Messages
37
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,536
There're a lot of algorithms available for division in Hardware.

Try the Newton Raphson Algorithms.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top