First real verilog program, synchronizing clock to seconds.

[epocaliptic]

So here is my code, this is the first thing I've done in verilog so take it easy on me if you can. I'm getting an error in quartus that states:

Error (10200): Verilog HDL Conditional Statement error at clock.v(12): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct.

here is my code.

Am I also on the right track if I want to synchronize a 50mhz clock to seconds?

By the way I know nothing is set to the outputs yet, I'll do that later.

module clock(clk,reset,KEY0,KEY1,sec,min,hour);
	input KEY0,KEY1,clk,reset;
	output sec,min,hour;
	
	//assuming clock is 50 mhz, so 1000mhz=1khz, and 1khz is 1 second, so 50 mhz=50,000 khz.
	reg [15:0] clk_counter;
	reg[5:0] seconds_counter;
	reg[5:0] min_counter;
	reg[4:0] hour_counter;
	always @(posedge clk or posedge reset)
	begin
		if (reset || hour_counter==5'b11000) //reset entire clock to zero with reset or with when clock hits 24
		begin
			clk_counter=16'b0000000000000000;
			seconds_counter=6'b000000;
			min_counter=6'b000000;
			hour_counter=5'b000000;
		end
		
		
		else if (min_counter==6'b110001 && seconds_counter==6'b110001)//incrementing hours at 59 minutes and 59 seconds
		begin
			clk_counter=16'b0000000000000000;
			hour_counter=hour_counter + 1;
			seconds_counter=6'b000000;		
			min_counter=6'b000000;
		end
		else if (seconds_counter==6'b110001)//incrementing minutes at 59 seconds
		begin
			clk_counter=16'b0000000000000000;
			min_counter=min_counter + 1;
			seconds_counter=6'b000000;
		end
		
		else if (clk_counter==16'b1100001101001111)//49,999 in binary, should increment seconds and then reset the counter.
		begin
			clk_counter=16'b0000000000000000;
			seconds_counter= seconds_counter + 1;
		end
			
		else
		begin
			clk_counter<= clk_counter + 1;
		end
	end
endmodule

Thank you for your time.

 

[poluekt]

Try to split if (reset || hour_counter==5'b11000) on 2 branches, because used asinc reset:

if (reset) //reset 
		begin
			clk_counter=16'b0000000000000000;
			seconds_counter=6'b000000;
			min_counter=6'b000000;
			hour_counter=5'b000000;
		end
else if (hour_counter==5'b11000)
		begin
			clk_counter=16'b0000000000000000;
			seconds_counter=6'b000000;
			min_counter=6'b000000;
			hour_counter=5'b000000;
		end
....

 

[epocaliptic]

thanks for your response poluekt,

but even if I take out the reset entirely and just leave (hour_counter==5'b11000) I still get the error.

 

[poluekt]

For sequential logic use non-blocking assignment <= instead blocking assignment =

 

[epocaliptic]

oh yes, I forgot to do that for most of them, thank you for reminding me.

But I don't think it will fix the error that I am getting in the if statement.

 

[epocaliptic]

got it working, thank you poluekt when i split it up into two if statements it seemed to work!