FIR filter using Distributed Arithmetic

Status
Not open for further replies.
V

vampiro

Newbie level 3
Joined
Feb 5, 2010
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,316
Im trying to implement an FPGA based FIR filter using Distributed arithmetic. I need to find a structure to implement. hope someone can help me out finding a schematic to implement
thanks [/quote]
 

first design an lut according to your filter cofficent(all possible combination to your bit pattern),then call to your values according to your input which is multiplierless method
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…