Hi all,
I want to design filter to implement on FPGA with a mentioned parameters in subject but when i am starting to design it on matlab fdatool, it gives very high order filter result, and when i decrease or set by myself upto 10 order its impulse response is not good as i want.
Any idea will be highly appreciable.
Regards,
Umair
You give the explanation in the question title. The minimal FIR filter order is related to the fs/fc ratio. With this sampling frequency, you can't make even a poor FIR filter with less than e.g. 500 or 1000 taps.
Possible solutions:
- design a multirate filter with decimation before the final filter
- design an IIR filter. It must have increased accumulator resolution (e.g. 10 extra bits) to handle the fs/fc range without dynamic loss.
Thanks for your reply, but what did on on fdatool is to shift filter level (fc) towards high frequency like 5MHz and it give magnitude response about -9dB on 300kHz but with high order and high pass filter.
it will be right ?? means for example in case of high pass filter officially i want to implement filter with same sampling rate, fc = 300kHz but i will take coeficients with fc = 5MHz or 3 MHz it will work fine??
apparently it will work. . .