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finfet xor netlist file, the result is not right

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suri123

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finfet xor netlist file ,result is not right

i have made xor file with use of ptm 45 nm file ,my result not correct ,plz help
file is below


Code:
* This is sub 45nm FinFET prdictive model 
.options post=2 brief


** subckt for NMOS **

.subckt DGNMOS NVd NVgf NVgb NVs

.include 'C:\Users\suresh\Downloads\Compressed\45nm_finfet

\soinmos1.pm'  * front soi model card
.include 'C:\Users\suresh\Downloads\Compressed\45nm_finfet

\soinmos2.pm'  * back soi model card

.param pnch = 2e16
.param len = 45e-9
.param ptox = 1.5e-9
.param ptsi = 8.4e-9
.param ptbox = 1.5e-9
.param npvthf0 = 0.31
.param npvthb0 = 0.31
.param esi = 11.7
.param eox = 3.9
.param nlambda1 ='(-1)*(ptox/(ptbox+ptsi/(esi/eox)))'
.param nlambda2 ='(-1)*(ptbox/(ptox+ptsi/(esi/eox)))'

.param delta1 = 0.008
.param delta2 = 0.008

.param Voff2=-0.09
.param N = 0.2
.param Vt = 0.0259
.param Voff1 = 0.0

mn1  NVd  NVgf1 NVs  0  nmos1 w=120e-9 l='len'
mn2  NVd  NVgb1 NVs  0  nmos2 w=120e-9 l='len'

En1 NVgf NVgf1 VOL = 'nlambda1*(-1*N*Vt*log(1+exp

((((nlambda2*(npvthb0-(v(NVd)-v(NVs))*delta2)+(npvthf0-(v

(NVd)-v(NVs))*delta1))/(1-(nlambda1*nlambda2))+Voff2)-(v

(NVgb)-v(NVs))-Voff1)/N/Vt))+N*Vt*log(1+exp((((nlambda2*

(npvthb0-(v(NVd)-v(NVs))*delta2)+(npvthf0-(v(NVd)-v(NVs))

*delta1))/(1-(nlambda1*nlambda2))+Voff2)-Voff1)/N/Vt))-

1*N*Vt*log(1+exp(((-1)*((nlambda2*(npvthb0-(v(NVd)-v(NVs))

*delta2)+(npvthf0-(v(NVd)-v(NVs))*delta1))/(1-

(nlambda1*nlambda2))+Voff2)-Voff1)/N/Vt))+N*Vt*log(1+exp((-

Voff1)/N/Vt)))'
En2 NVgb NVgb1 VOL = 'nlambda2*(-1*N*Vt*log(1+exp

((((nlambda1*(npvthf0-(v(NVd)-v(NVs))*delta1)+(npvthb0-(v

(NVd)-v(NVs))*delta2))/(1-(nlambda1*nlambda2))+Voff2)-(v

(NVgf)-v(NVs))-Voff1)/N/Vt))+N*Vt*log(1+exp((((nlambda1*

(npvthf0-(v(NVd)-v(NVs))*delta1)+(npvthb0-(v(NVd)-v(NVs))

*delta2))/(1-(nlambda1*nlambda2))+Voff2)-Voff1)/N/Vt))-

1*N*Vt*log(1+exp(((-1)*((nlambda1*(npvthf0-(v(NVd)-v(NVs))

*delta1)+(npvthb0-(v(NVd)-v(NVs))*delta2))/(1-

(nlambda1*nlambda2))+Voff2)-Voff1)/N/Vt))+N*Vt*log(1+exp((-

Voff1)/N/Vt)))'
.ends





** sub ckt for PMOS **

.subckt DGPMOS PVd PVgf PVgb PVs

.include 'C:\Users\suresh\Downloads\Compressed\45nm_finfet

\soipmos1.pm' * front soi model card
.include 'C:\Users\suresh\Downloads\Compressed\45nm_finfet

\soipmos2.pm' * back soi model card

.param pnch =2e16
.param len = 45e-9
.param ptox = 1.5e-9
.param ptsi = 8.4e-9
.param ptbox = 1.5e-9
.param ppvthf0 = -0.25
.param ppvthb0 = -0.25
.param esi = 11.7
.param eox = 3.9
.param plambda1 ='(-1)*(ptox/(ptbox+ptsi/(esi/eox)))'
.param plambda2 ='(-1)*(ptbox/(ptox+ptsi/(esi/eox)))'

.param pdelta1 = 0.008
.param pdelta2 = 0.008

.param Voff2 = 0.12
.param N = 0.2
.param Vt = 0.0259
.param Voff1 = 0.0

mp1  PVd  PVgf1 PVs  n1  pmos1 w=300e-9 l='len'
mp2  PVd  PVgb1 PVs  n1  pmos2 w=300e-9 l='len'

vvdd n1 0 1

Ep1 PVgf PVgf1 VOL = 'plambda1*(-1*(-1*N*Vt*log(1+exp((-1*

((plambda2*(ppvthb0-(v(PVd)-v(PVs))*pdelta2)+(ppvthf0-(v

(PVd)-v(PVs))*pdelta1))/(1-(plambda1*plambda2))+Voff2)+(v

(PVgb)-v(PVs))+Voff1)/N/Vt))+N*Vt*log(1+exp((-1*((plambda2*

(ppvthb0-(v(PVd)-v(PVs))*pdelta2)+(ppvthf0-(v(PVd)-v(PVs))

*pdelta1))/(1-(plambda1*plambda2))+Voff2)+Voff1)/N/Vt))-

1*N*Vt*log(1+exp((((plambda2*(ppvthb0-(v(PVd)-v(PVs))

*pdelta2)+(ppvthf0-(v(PVd)-v(PVs))*pdelta1))/(1-

(plambda1*plambda2))+Voff2)+Voff1)/N/Vt))+N*Vt*log(1+exp

((Voff1)/N/Vt))))' 
Ep2 PVgb PVgb1 VOL = 'plambda2*(-1*(-1*N*Vt*log(1+exp((-1*

((plambda1*(ppvthf0-(v(PVd)-v(PVs))*pdelta1)+(ppvthb0-(v

(PVd)-v(PVs))*pdelta2))/(1-(plambda1*plambda2))+Voff2)+(v

(PVgf)-v(PVs))+Voff1)/N/Vt))+N*Vt*log(1+exp((-1*((plambda1*

(ppvthf0-(v(PVd)-v(PVs))*pdelta1)+(ppvthb0-(v(PVd)-v(PVs))

*pdelta2))/(1-(plambda1*plambda2))+Voff2)+Voff1)/N/Vt))-

1*N*Vt*log(1+exp((((plambda1*(ppvthf0-(v(PVd)-v(PVs))

*pdelta1)+(ppvthb0-(v(PVd)-v(PVs))*pdelta2))/(1-

(plambda1*plambda2))+Voff2)+Voff1)/N/Vt))+N*Vt*log(1+exp

((Voff1)/N/Vt))))'
.ends




xp1 a0bar a0 a0 vvdd DGPMOS
xp2 b0bar b0 b0 vvdd DGPMOS
xp3 l1 a0 a0 vvdd DGPMOS
xp4 l1 b0 b0 vvdd DGPMOS
xp5 s0 a0bar a0bar l1 DGPMOS
xp6 s0 b0bar b0bar l1 DGPMOS
xn1 a0bar a0 a0 vss DGNMOS
xn2 b0bar b0 b0 vss DGNMOS
xn3 s0 a0 a0 l2 DGNMOS
xn4 l2 b0 b0 vss DGNMOS
xn5 s0 a0bar a0bar l3 DGNMOS
xn6 l3 b0bar b0bar vss DGNMOS




*CL s0 0 10f
VFG1 a0 0 pulse 0 1 600p 10p 10p 2n 5n

VFG3 b0 0 pulse 0 1 600p 10p 10p 2n 5n

VSS gnd 0 0

*vfg vg1 0 0.1
vvdd vdd 0 1



.OPTION POST

*.option method=gear

*.DC VFG 0 1 0.001
*
*.plot DC V(Out)

.tran 0.1p 50n 0.01p

.print tran V(s1)


.end
 
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