Finfet different vt

[macrodesigner]

Hi All,

I am trying to design SRAM memories in finfet nodes. i can see there are multiple vt types in library ( svt,lvt,ulvt). what parameter causes to have different in finfet devies.
I know oxide thickness (tox) is one parameter and not sure about doping dependence ( this was the case in planar).

trying to understand first order effects which lead to multiple vt in any technology offering.

Thanks
---

 

[ThisIsNotSam]

multiple vt is not a new finfet thing, it has existed for a long time. a simple google search will tell you that lvt=fast but leaky, hvt=slow but power efficient.

 

[macrodesigner]

Thanks for reply @ThisIsNotSam. My question is more inclined towards what causes different vt in finfet nodes other than tox.

 

[dick_freebird]

Core tox is the same for all VT versions. You could
tell this by the voltage rating(s). There's probably
an I/O tox which is higher. Not likely more than two
altogether. Consider the tox and the threshold
implants as orthogonal dimensions.

 

[macrodesigner]

Thanks, @dick_freebird after you mentioned about threshold implantation layer.
I got this patent from TSMC regarding the different vt fabrication process.
https://patentimages.storage.googleapis.com/e5/25/57/d1c96b8c9f5ca3/US20170033106A1.pdf

Thanks
Sushil

 

[timof]

Vt in FinFETs is controlled not by the channel doping (as in planar MOSFETs), but by the gate (metal) material choice.
Some technologies have up to 6 different Vt's (three for each type - p- and n-type), some - up to 8 Vt's.