FinFet 32nm invertor in Cadence

[Annee]

We have been designing a finfet_32nm invertor in cadence as part of our research. However we are not getting the desired output

this is the invertor we designed. the out put we got is

we have currently given Vds values as 1V,0.6V,0.8V but none of these values also worked. Kindly suggest me wether there is an error in the design or the values we have provided

Thank you

 

[dick_freebird]

The plot is too washed-out to resolve much
numerically, but it appears that there is a
circuit discontinuity to me - the capacitive
looking glitch, and failure to ever go high.

I'd begin with sanity-checking the symbol to
SPICE pin and parameter-passing (like, is the
netlist order in the Cadence symbol putting
D, G, S, B (e?) in correct order to the netlist
line?).

Then, if you're sure connectivity is passed all
through the hierarchy correctly, try a pair of
N, P FET I-V sweeps looking for classical FET
ID-VD, ID-VG behaviors.