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Finding frequency of operation in synopsys DC

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anjyothiswaroop

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Hi,
I want to find frequency of operation for my_design at (i)Min area (ii)Max performance.

And my synthesis script is as follows:

analyze -f VHDL lib -work my_design.vhd
elborate my_design -library work
create_clock -name "clock1" -period N clk
set_max_area 0.0
insert_clock_gating
link
uniquify
compile -incremental -map_effort high
report_constraint
report_area
report_timing

For finding freq at min area above script was used with
a) removing create clk cmd: total area=10625.101429 , data arrival time=3.28
b) clk period as 50 ns : total area=10923.217473 , data arrival time=3.14
c) clk period as 10 ns : total area=10803.265446 , data arrival time=3.13
d) clk period as 7 ns : total area=10779.980644 , data arrival time=3.84
e) clk period as 3.84 ns : total area=10780.333444 , data arrival time=3.64

I am working on maximum perofromance with removing set_max_area command and set compile map_effort low.
a) clk period as 50 ns : total area=10923.217473 , data arrival time=3.87
b) clk period as 25 ns : total area=10923.217473 , data arrival time=3.87
c) clk period as 0 ns : total area=13494.776588 , data arrival time=1.82

I am a beginner in Design compiler.I am not able to make any inference with these results and don't understand how DC is optimising the design. Am Iapproaching the problem in the right manner? Any suggestions is welcome
 

kornukhin

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There are few suggestions:
- when you set area to 0, DC trying to optimize slack (you have enough margin) and then minimizes area.
- when area is unconstrained (a,b), DC trying to fix critical pathes (which aren't present)
- when area is unconstrained (c), DC optimizing critical paths until it reaches minimum total negative slack. I think you design contain some high fanout nets, fixing them DC inserts some additional logic (to decrease delay), but area grows up.
 
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