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FIFO Xilinx Core Generator

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kirill

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Hello!
I am a bit confused about this two signals in FIFO core : "rd_data_count" and "wr_data_count". For what this option in core generator exists? I mean why it is not enough to use only one signal "data_count"? What situation could occur when i will need both of them?
Thank you!
 

Scrts

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When You use DCFIFO (dual clock fifo). When the read or/and write clocks are different frequency, You can check the full/empty flag and control the write and read flags accordingly.
 

kirill

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But the size of the buffer does not change, if i use different frequencies
 

mrflibble

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When you use two different clocks and different read and write widths, I'm sure you will see the difference.

But even with the same widths, but different clocks the 2 counts are useful. The rd_data_count is updated on the read clock, and wr_data_count is updated on the write clock.

Generally I find that for functionality during synthesis I don't really need the data_count. Empty and full flags turn out to be enough. BUT, for simulation having rd_data_count and wr_data_count available are turns out to be very useful. So while I only need empty/full for synthesis, I still enable rd_data_count and wr_data_count as well because it makes simulation and debugging a lot easier.

hope that helps
 
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Scrts

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It is more useful to use almost_full or almost_empty flags as data is never corrupted or gone. This also can be achieved by using usedw[width-1:0] output. I am talking about Altera DCFIFO here, but I am sure, the same is on Xilinx.
 

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It is more useful to use almost_full or almost_empty flags as data is never corrupted or gone. This also can be achieved by using usedw[width-1:0] output. I am talking about Altera DCFIFO here, but I am sure, the same is on Xilinx.

For synthesis I agree that "almost_full" and "almost_empty" are far more useful than "rd_data_count" and "wr_data_count". The added value of "almost_full" above "full" of course is a bit relative. But it does give you 1 more cycle, so that makes things a bit easier...

For simulation and debug reasons I still use "rd_data_count" and "wr_data_count" in addition to "empty" and "full" flags. So far I have not found any drawbacks to that...

And yeah, it's the same on xilinx, since that's what I'm talking about. :)
 

kirill

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So, in conclusion of the thread read and write data count need in such situations(synthesis) :
1. different frequencies on wr part and rd part of the fifo for correct update of the count value.
2. if different write and read data width applies.
3. or 1 and 2 points together.
Yes?
 

mrflibble

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That's a bit too ambiguous to say yes or no to as a definite conclusion. Could you please clarify, because I don't quite follow what you mean exactly.
 

mrflibble

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I am confused in general on a daily basis, but that is beside the point. ;)

What I mean is that your sentences are a bit too non-specific and ambiguous to pin down an exact meaning. And ambiguity is never a good starting point for a summary.

Could you maybe rephrase it using completely new and different sentences? Thanks.
 

kirill

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I agree with You in "ambiguity is never a good starting point for a summary". "Clarify the meaning of words - and you will save mankind from half errors" Rene Descartes. This is may be not exact quote, this is translation from Russian. I am not so good in English, so may be this is the reason of ambiguity of points above)
 

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