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FIFO with dual clock design

Thread starter RTL2GDSII
Start date Feb 25, 2003

Status: Not open for further replies.

Feb 25, 2003

#1

R

RTL2GDSII

Member level 1

I need a synthesizable code for FIFO with dual clock (input one clcok. output another clock domain).
Anybody can help ?

Feb 25, 2003

#2

I

it_boy

Full Member level 3

asynchronous fifos

Check out the following..
http://www.geocities.com/deepakgeorge2000/vlsi_book/Asynch1.pdf
http://www.geocities.com/deepakgeorge2000/vlsi_book/async_fifo2.pdf

Jul 7, 2003

#3

A

allegro

Member level 1

It is useful

Status: Not open for further replies.

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