Advanced Member level 3
A data of width 8 is being written in the FIFO at a clock frequency f1. The data is read from the FIFO with a width of 16 at a frequency f2. Will not in this case functionality be affected because data of 8 bit is coming at write side. But the data is only being read with width 16 bit and then processed in the new clock domain at 16 bits instead of 8 bits as the width as it is written in the FIFO. Will not it affect the functionality of the whole system?