Fifo scheduler design

[Muthumari]

this my coding for designing fifo buffer scheduler for 8 resource in cdma network.... any one help me to finish my project..... here i attach coding then the following error was occur pls correct it and send to me......
module Buffer(clk,rst,data,d_in,sour_addr,dest_addr,valid_bit,d_out,full,empty);
input clk;
input rst;
input [2:0]sour_addr;
input [2:0]dest_addr;
input valid_bit;
input [7:0]data;
input [14:0]d_in;

parameter packsize = 15;

output reg [14:0]d_out;
output full;
output empty;
reg [14:0]temp;

assign temp = valid_bit;
assign [3:1]temp = [2:0]sour_addr;
assign [11:4]temp = [7:0]data;
assign [14:12]temp = [2:0]dest_addr;

assign full = (temp == packsize);
assign empty = (temp == 0);

always @ (posedge clk or posedge rst)
begin
if(d_in == 0)
begin
d_out[0] = valid_bit;
end
else if(d_in[0] == 1)
begin
d_in[0] = 1'b0;
end
if (empty == 1)
begin

d_out[1] = temp[1];
d_out[2] = temp[2];
d_out[3] = temp[3];
d_out[4] = temp[4];
d_out[5] = temp[5];
d_out[6] = temp[6];
d_out[7] = temp[7];
d_out[8] = temp[8];
d_out[9] = temp[9];
d_out[10] = temp[10];
d_out[11] = temp[11];
d_out[12] = temp[12];
d_out[13] = temp[13];
d_out[14] = temp[14];
end
else if (full == 1)
begin
packsize = 14'b00000000000000;
end
end
endmodule


ERROR:HDLCompilers:26 - "Buffer.v" line 37 unexpected token: '['
ERROR:HDLCompilers:26 - "Buffer.v" line 37 unexpected token: '['
ERROR:HDLCompilers:26 - "Buffer.v" line 37 expecting ';', found ':'