FIFO or delay for 500 MSPS ADC testing

[JGLeong]

Hi there,

I'm new here, and don't have a strong electronic background.

I wish to evaluate the performace of a TI ADS5463 12 bit ADC at 500MSPS.

However, my logic analyzer can only do 200

Is there a way I can slowdown the output / implement a some sort of FIFO (like those from AD) that will capture samples for analysis at a slower speed ?
(I do need the adc sampling at 500)

Thanks for your help.

JG