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[SOLVED] FIFO o/p frequency getting reduced by 2

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Advanced Member level 1
May 22, 2013
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I was testing the aurora core from Virtex 7 to Artix 7 that i have designed.So in the Virtex 7 design a tx_fifo is present into which Virtex data is dumped which has to be sent to A7.

Basic Test Case:
So a basic test was to test using test pattern of ADC which i have.I could see this test pattern in A7.So the core is ok,i guess.

Now to test for large number of samples to see if i am losing any samples,i am giving 5 MHz RF(low frequency sine wave) to ADC which dumps sampled data into tx_fifo.Ideally i should get this 5 MHz sine wave in Artix also.

tx_fifo details : in : 128 bit vector out : 32 bit vector.

On ILA i'm debugging both these 128 & 32 bit vector.After exporting -> Matlab -> plotting in matlab i'm noticing that the frequency of sine wave has reduced by 2.

128 bit vector is ADC o/p & 32 bit vector is aurora core i/p.We should be getting same frequency for FIFO i/p & o/p

Why is this ?
Last edited:


Your information is not very clear.
Analog input to ADC is 5MHz sine wave?
--> ADC ---> FPGA ---> FIFO ---> ???

We should be getting same frequency for FIFO i/p & o/p
Do you mean digital data rate or analog frequency? If analog frequency: How do you test it? DAC, display?

what´s your ADC sample frequency?
(maybe it´s 7.5MHz??)


You never defined how the ADC data is formatted in the 128-bit vector and in the 32-bit vector, perhaps you've done the math wrong and have an incorrect ratio somewhere.

use a ramp pattern that is internally generated. you'll see skips/repeats in the data easily. You can also check for a ramp pattern in the artix device and count the error count and error rate. if you don't see these then check MATLAB. It's odd to get a half frequency without also getting obvious data errors.

After that, double check the infrastructure and make sure all clocks are as expected. Some aurora cores make use of unexpected clock rates, so verify the rates in the system vs the rates in the example design. (you can also implement the example design if all else fails)

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