FIFO FWFT problem. First word twice.

[peter.m]

Hi,

in FIFO First-Word Fall-Through, when I check if it is not empty (empty = 0) and then in this case set '1' on read_enable together with assigning data output to some signal ( at the same time), I should get correct value? And if I check in the next step that FIFO is still not empty and do the same, I should get next value?

I ask because my FIFO release twice the first value. I sent to it bytes like [1 2 3 4 5] and I get [1 1 2 3 4]. What can be wrong?

I use Spartan 3 and FIFO from IP cores with read mode FWFT.

Here is part of my code:

				when STATE1 =>
					if (rx_fifo_rdempty = '0') then
						address (31 downto 24) <= rx_fifo_q;
						rx_fifo_rdreq <= '1';
						state <= STATE2;
					end if;
				
				when STATE2 =>
					if (rx_fifo_rdempty = '0') then
						address (23 downto 16) <= rx_fifo_q;
						rx_fifo_rdreq <= '1';
						state <= STATE3;
						LED <= rx_fifo_q;
					end if;

In both states I get on LED the same (here is led only in second state). When it is then in similar STATE3 I get there that what I'd like to get in STATE2.

 

[TrickyDicky]

are you sure you didnt write the first value twice in the first place? what FIFO is it? a custom one or the XIlinx one?

 

[peter.m]

It is Xilinx FIFO.
I'm not quite sure. I use FTDI and writing code to FIFO from opencores.org (FT2232H USB Avalon Core):

rx_fifo_rdclk <= clk;
tx_fifo_wrclk <= clk;

-- U S B side
rx_fifo_wrclk <= usb_clock;
tx_fifo_rdclk <= usb_clock;


ft2232_tx_please <= '1' when usb_txe_n = '0' and tx_fifo_rdempty = '0' and ft2232_wait = 1 else '0';
ft2232_rx_please <= '1' when usb_rxf_n = '0' and rx_fifo_wrfull = '0' else '0';


ft2232_tx_fifo_read <= '1' when ft2232_tx_please = '1' else '0';
ft2232_rx_fifo_write <= '1' when ft2232_bus_oe_mode > 1 and ft2232_rx_please = '1' and ft2232_tx_please = '0' else '0';

tx_fifo_rdreq <= ft2232_tx_fifo_read;
rx_fifo_wrreq <= ft2232_rx_fifo_write;

usb_rd_n <= '0' when ft2232_rx_fifo_write = '1' else '1';
usb_wr_n <= '0' when ft2232_tx_fifo_read = '1' else '1';
usb_oe_n <= '0' when ft2232_bus_oe_mode > 0 else '1';
usb_data <= tx_fifo_q when ft2232_bus_oe_mode = 0 else (others => 'Z');
rx_fifo_data <= usb_data when ft2232_bus_oe_mode > 0 and usb_rxf_n = '0' else (others => '0');


-- Handle FIFOs to USB2232 in synchronous mode
process (usb_clock)
begin

	if rising_edge(usb_clock) then
		-- Bias TX over RX
		if (ft2232_tx_please = '1' or ft2232_rx_please = '0') then

			ft2232_bus_oe_mode <= 0;
			
			if (usb_txe_n = '0' and tx_fifo_rdempty = '0') then
				ft2232_wait <= ft2232_wait + 1;
			else
				ft2232_wait <= 0;
			end if;
		elsif (ft2232_rx_please = '1') then

			ft2232_wait <= 0;
			
			-- Handle bus turn-around. Negate OE (and for atleast 1 clock)
			if (ft2232_bus_oe_mode < 3) then		
				ft2232_bus_oe_mode <= ft2232_bus_oe_mode + 1;
			end if;

		end if;

	end if;		

end process;

 

[j_andr]

your 'rx_fifo_rdreq' is set to '1' one clock cycle
too late; [or you read fifo one cycle too fast]

when you are in 'STATE1':
on clock slope '0' you latch fifo output ['8x1'],
set read request 'rx_fifo_rdreq' to '1',
[but fifo output is still '8x1'],
and go to 'STATE2';

on clock slope '1':
you latch again fifo output '8x1',
fifo out changes to '8x2'
the fsm goes to 'STATE3'

j.a

 

[peter.m]

I don't understand.
Xilinx docs says that data is available when I set request for it. So I thought that it happens simultaneously:

address (31 downto 24) <= rx_fifo_q;
						rx_fifo_rdreq <= '1';

 

[j_andr]

I don't understand.
Xilinx docs says that data is available when I set request for it.
So I thought that it happens simultaneously

first written word is available at fifo output immediately [almost];
to get the second the fifo has to 'see' read request active
on a clock edge;
but on the same edge, when read request is active, you register
again fifo output, the 'old' value;

            __    __    __
clock    __/  \__/  \__/  \__
                   ___________
rd_rqst __________/

        _______________________
fifo_q    01     01     X   02
        -----------------------

have you simulated the design ?

j.a

 

[peter.m]

Ok, now I understand but don't know why it happens, why only on the second value.
No, I didn't simulated it and yes, I know it is wrong way, against good design practice. I though that it will be simple.

 

[j_andr]

Ok, now I understand but don't know why it happens

rearrange the piece:

 when STATE1 =>
   if (rx_fifo_rdempty = '0') then
     address (31 downto 24) <= rx_fifo_q;
     rx_fifo_rdreq <= '1';
     state <= STATE2;
   end if;

to:

 when STATE1 =>
   if (rx_fifo_rdempty = '0') then
     rx_fifo_rdreq <= '1';
     if ( rx_fifo_rdreq = '1' ) then
       address (31 downto 24) <= rx_fifo_q;
       state <= STATE2;
     end if
   end if;

the same for STATE2;

check in simulation difference of timing of rx_fifo_rdreq
and latching data in address

j.a

 

[peter.m]

Now I see. I thought that it will be some delay, but it takes two clock cycles in first state and one cycle in next states.
Thank you very much for your help.