FIFO Coregen problem

[Sugam]

Hi,
I am trying to simulate a 1024x16 FIFO using coregen using VHDL. I have declared the entity myself and copied the remaining code from .vho file of the coregen (as explained in various online tutorials). Although my code is being sythesized correctly, in simulation, I am getting a warning like:-

WARNING:Simulator:29 - at 0 ns: Warning: No entity is bound for inst

and the output is coming 'uninitialized' (red lines)
Following is the code:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity fifo2_my is

port (
clk: IN std_logic;
din: IN std_logic_VECTOR(15 downto 0);
rd_en: IN std_logic;
rst: IN std_logic;
wr_en: IN std_logic;
data_count: OUT std_logic_VECTOR(9 downto 0);
dout: OUT std_logic_VECTOR(15 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
overflow: OUT std_logic;
valid: OUT std_logic;
underflow: OUT std_logic;
wr_ack: OUT std_logic);
end fifo2_my;

architecture Behavioral of fifo2_my is

component fifo2
port (
clk: IN std_logic;
din: IN std_logic_VECTOR(15 downto 0);
rd_en: IN std_logic;
rst: IN std_logic;
wr_en: IN std_logic;
data_count: OUT std_logic_VECTOR(9 downto 0);
dout: OUT std_logic_VECTOR(15 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
overflow: OUT std_logic;
valid: OUT std_logic;
underflow: OUT std_logic;
wr_ack: OUT std_logic);
end component;

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo2: component is true;


UUT : fifo2
port map (
clk => clk,
din => din,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
data_count => data_count,
dout => dout,
empty => empty,
full => full,
overflow => overflow,
valid => valid,
underflow => underflow,
wr_ack => wr_ack);

end Behavioral;

Plz help!!

 

[aruipksni]

Hi,
I am trying to simulate a 1024x16 FIFO using coregen using VHDL. I have declared the entity myself and copied the remaining code from .vho file of the coregen (as explained in various online tutorials). Although my code is being sythesized correctly, in simulation, I am getting a warning like:-

WARNING:Simulator:29 - at 0 ns: Warning: No entity is bound for inst

and the output is coming 'uninitialized' (red lines)
Following is the code:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity fifo2_my is

port (
clk: IN std_logic;
din: IN std_logic_VECTOR(15 downto 0);
rd_en: IN std_logic;
rst: IN std_logic;
wr_en: IN std_logic;
data_count: OUT std_logic_VECTOR(9 downto 0);
dout: OUT std_logic_VECTOR(15 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
overflow: OUT std_logic;
valid: OUT std_logic;
underflow: OUT std_logic;
wr_ack: OUT std_logic);
end fifo2_my;

architecture Behavioral of fifo2_my is

component fifo2
port (
clk: IN std_logic;
din: IN std_logic_VECTOR(15 downto 0);
rd_en: IN std_logic;
rst: IN std_logic;
wr_en: IN std_logic;
data_count: OUT std_logic_VECTOR(9 downto 0);
dout: OUT std_logic_VECTOR(15 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
overflow: OUT std_logic;
valid: OUT std_logic;
underflow: OUT std_logic;
wr_ack: OUT std_logic);
end component;

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo2: component is true;


UUT : fifo2
port map (
clk => clk,
din => din,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
data_count => data_count,
dout => dout,
empty => empty,
full => full,
overflow => overflow,
valid => valid,
underflow => underflow,
wr_ack => wr_ack);

end Behavioral;

Plz help!!

I guess it is some folder problem.
Modelsim look for this inst in work folder but
It is probebly located someplace else. Probebly
In coregen project folder.

 

[Sugam]

my .xco file is there in source library-> work folder along with my .vhd file i created.

 

[aruipksni]

I hope you remember also to compile the
Fifo vhd file also.

 

[Sugam]

I did nothing to the .vhd file created by coregen. I made a new .vhd file in which i incorporated the portion of code given in .vho file of coregen. This is the only file i synthesized.
My method is fine, right?

 

[aruipksni]

I did nothing to the .vhd file created by coregen. I made a new .vhd file in which i incorporated the portion of code given in .vho file of coregen. This is the only file i synthesized.
My method is fine, right?

You must compile it to modelsim.

 

[Sugam]

Looks like i don't have modelsim.exe installed. By the way, why is it necessary to compile through modelsim and not ISE simulator?

 

[rajavel.rv]

I think its having reset problem; first u check your FIFO reset it '0' or '1'; and it sync or async reset, and your global reset is asyn means given fifo reset after 100 clk cycle delay;

 

[ads-ee]

Looks like i don't have modelsim.exe installed. By the way, why is it necessary to compile through modelsim and not ISE simulator?

aruipksna doesn't understand you are not using Modelsim. You did not specify in post #1 you were having problems with the ISIM (ISE simulator).

Did you use the default directory that ISE uses for coregen? If not you may have to add the directory to the search path for the ISE project. Check if in the project hierarchy that the core shows up under your top level file. You shouldn't see any ! when you expand the hierarchy.

Regards