FIFO architecture and flipflops

[ASIC_int]

I know how FIFO is realized by DPRAM. But FIFO is also realized by flipflops. Can anybody provide me a document that write about how a FIFO architecure looks with flipflops or explain about this id you do not have any document? I had a document on how FIFO architecture looks with DPRAM.

Please provide me a document which write basics about FIFO for beginners who do not know what FIFO is.

 

[mturna]

**broken link removed** this may help you

 

[rca]

I don't see exactly your issue, the flop will replace on bit of the DPRAM (for dual port RAM, I expect), and you need to code the dual access of the flop, and that's it!?

 

[vijayatmu]

Hello RCA,

What is a dual access flop. Is it a read and write at the same time?

Can you please share any material that you may have on the design of a dual access flop.

Vijay

 

[rca]

the read process will be combinational, so both ports could read a flop in same time.
If you allow both port to write at same time, you need to specify some priority or ignore both write request.

ENTITY DPRAM_trial
PORT
nreset : IN STD_LOGIC; -- asynchronous low active reset
clk : IN STD_LOGIC; -- system clock
-- first port
port_1_cs : IN STD_LOGIC; -- port 1 chip select
port_1_wr : IN STD_LOGIC; -- port 1 write condition
port_1_rd : IN STD_LOCIG; -- port 1 read condition
port_1_address : IN STD_LOGIC; -- port 1 address
port_1_data_wr : IN STD_LOGIC; -- port 1 data write
port_1_data_rd : OUT STD_LOGIC; -- port 1 data read
-- second port
port_2_cs : IN STD_LOGIC; -- port 2 chip select
port_2_wr : IN STD_LOGIC; -- port 2 write condition
port_2_rd : IN STD_LOCIG; -- port 2 read condition
port_2_address : IN STD_LOGIC; -- port 2 address
port_2_data_wr : IN STD_LOGIC; -- port 2 data write
port_2_data_rd : OUT STD_LOGIC; -- port 2 data read
);

ARCHITECTURE example IS
BEGIN
p_sync: process(nreset, clk)
BEGIN
IF nreset='0' THEN
mem <= '0';
elsif clk'event AND clk='1' THEN
-- port_1 has predominant versus port_2
IF port_1_cs='1' AND port_1_address='1' AND port_1_wr='1' THEN
mem <= port_1_data_wr;
ELSIF port_2_cs='1' AND port_2_address='1' AND port_2_wr='1' THEN
mem <= port_2_data_wr;
END IF;
END IF;
END PROCESS p_sync;

p_asyncROCESS (port_1_cs, port_1_rd, port_1_address, port_2_cs, port_2_rd, port_2_address)
BEGIN
-- first port
port_1_data_rd <= '0'; -- default value
IF port_1_cs='1' AND port_1_rd='1' THEN
IF port_1_address='1' THEN port_1_data_wr <= mem; END IF;
END IF;
-- second port
port_2_data_rd <= '0'; --default value
IF port_2_cs='1' AND port_2_rd='1' THEN
IF port_2_address='1' THEN port_2_data_wr <= mem; END IF;
END IF;
END PROCESS p_async;

END try;

in this quick example, the first port has the priority over the port 2, in the writing condition.

after you could used a case versus IF for the address section.

if I will wrote the code, I will used "vectorisation", to use FOR GENERATE for the read process, because there is two times the same process.

This code only replace the memory element, the fifo logic could be outside, to easily swap between a real memory or a flop instantiation.
The nreset signal could not be mandatory, depending of your guide line, or the area trade off (look at your std cell, and you will see some "big reduction of area/power" by using flop without reset versus real memory)

Is it what you look for?

 

[ASIC_int]

rca

In a one bitcell of a DPRAM there is a Wordline line and bit and bitbar line also. To what pins of a flipflop will you map this wordline, bit line and bitbarline. It is better if a architecture is obtained in terms of documentation.

Regards

 

[rca]

sorry for my simple example, but you could increase port_1/2_address size, as also the port_1/2_data_wr/rd, to be like a memory.

 

[vijayatmu]

RCA,

Thank you for the code for the dual access flop. Is there change of data contention happen when both read and write control signal happen at the same time. This is given that read is async and write is synchronous with the clock. Unless the control unit of the fifo handles it in such a way that control signal can never fire at the same time.

Regards,
Vijay

 

[lostinxlation]

RCA,

Thank you for the code for the dual access flop. Is there change of data contention happen when both read and write control signal happen at the same time. This is given that read is async and write is synchronous with the clock. Unless the control unit of the fifo handles it in such a way that control signal can never fire at the same time.

Regards,
Vijay

Designing a fifo with a dual port memory is a little bit of challenge depending on how you want to treat the data in the memory. Like you write through port1 and that data might be destroyed by another write operation through port2. If you don't wanto destroy that data, you may need to increment wr_ptr2 in a way to skip the already written location or you may need to maintain two separate data sections where each of them is controlled by the pointers belonging to each port and make sure they never overlap. Considering the role of FIFO, I cannot find any applications that utilize the a dual port memory as a FIFO. If I need to feed the fifo from two sources, I'd have some small logic that serializes the 2 write requests to a single one before feeding FIFO with it or have separate FIFOs.

I'm fairly certain that whoever started this thread didn't mean a dual port memory even though he referred to a dual port memory.

 

[rca]

Hi lostinxlation,

As already mention, my code only replace the memory element, and the FIFO logic is not inside this code, so the conflict or other stuff is not here.

 

[ASIC_int]

rca

You still did not reply to my query

In a one bitcell of a DPRAM there is a Wordline line and bit and bitbar line also. To what pins of a flipflop will you map this wordline, bit line and bitbarline. It is better if a architecture is obtained in terms of documentation.

Regards

 

[rca]

if you thing at what's mean word & bit lines. That' mean just select an address or a bit in a word.
my example only present one bit, the smalest element, so you increase the data out/in size as the address to be able to add word / bit lines
regards
Régis

 

[lostinxlation]

I don't know why the OP thinks everything from SRAM can be mapped to flops.

First, he needs to understand how memory works, and he would know why a bit line has complementary signals. Then he would know that complementary signals on std cell base design is virtually non-existent.