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fibonacci ring oscillator design problem

shockingshockley

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Hello! I am currently designing a Fibonacci ring oscillator as shown in the schematic. My input is a clock with a frequency 0f 30 MHz. However, my output during simulations is just a negated or inverted output with glitches. I am expecting a chaotic or random output. Please help me what is the possible cause of this unsuitable output. Do I need to put a resistor-capacitor RC network between inverter stages just like a normal ring oscillator? Thanks in advance.
 

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SunnySkyguy

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The schematic is not clear, but looks like an asynchronous ring generator intended to have maximal length sequences with pseudo-random inversions.

Start with your basic ring generator with negative feedback. and get it to oscillate at max frequency with an odd number of inverters
1632660426792.png
It appears you may have some UHF oscillations XOR'd with 100 MHz. (20 cycles in 200 ns = 100M) I think you want the harmonics of your input to be injection locked to the ring oscillator. Start with a ring Osc. then injection locked with 1 XOR from the harmonics, then add the string of delays for white noise. I'm not sure but maybe you just have to invert your input pulses. There is a reason for this, due to parity or total number of inverters in your loop.
 
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shockingshockley

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Hello. I found a basic ring oscillator. I want to clarify if R1 and C1 is required for the ring oscillator to function?
1632731928303.png



So do I need to put R and C here in my fibonacci ring oscillator?
1632732033472.png
 

SunnySkyguy

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The Rds and Ciss are the elements of the Ring Oscillator with propagation delay, but f1 in Fig 5, is toggling between positive feedback (latched) and negative feedback (oscillating from loop delay). Why ? This may explain
--- Updated ---

You know the Barkhausen criteria for oscillation that the loop gain at 180 deg. phase shift for an inverter needs to be >=1. In Falstad's Simulation, The inverters are ideal 0 Ohms so you must add RdsOn as a series R for the logic family and Vdd chosen. But the slew rate is user defined in each part's property. Slew rate means BW=0.35/Tr but if Ron is 0 then the gain is infinite so it oscillates in one state. Not the same as your situation, but similiar. https://www.edaboard.com/threads/design-of-2-stage-opamp-350nm.399713/#post-1720526


Therefore, for a ring oscillator to work properly the number of inverters in the 1st feedback loop, must give adequate delay equivalent to RC , this determines if it oscillates or just settles to DC = Vdd/2 from negative FB and latches from positive FB.

(Caveat: I"ve never fully analyzed your fibonacci osc.,) Others may have better insight. or read the researchgate article ( free registration)
 
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BradtheRad

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* Consider using op amps which may have a built-in slew rate (perhaps user adjustable). The slew rate creates a delay effect.
Configure to invert signal. Or schmitt triggers might do the job.
(Example, in Falstad's 741 op amp, there is a single capacitor in the internals. Increasing the cap value lengthens transition time.)

* When I use invert-gates simulating sequencers (chasers, ring counters), I find it improves reliability to put the RC delay at every gate's input. Otherwise it's hard to prevent the circuit from lapsing into unwanted two-state oscillation mode.

* Sometimes I must add an extra invert-gate (two gates in a row) in order to have the proper number of polarity inversions.

* Sometimes it helps to apply 1/2 supply V through a high-ohm resistor to each input. (Reason: 1/2 supply V is the threshold around which invert-gates change state.)

* Also try grounding the first input as you power up. Admit several preliminary clock pulses until the entire ring of devices is set to the same state. Then connect the first input to the final output. If you're lucky you get desired behavior (that is, one and only one change of state rotating through the devices).
 

SunnySkyguy

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