Junior Member level 3
Hello! I am currently designing a Fibonacci ring oscillator as shown in the schematic. My input is a clock with a frequency 0f 30 MHz. However, my output during simulations is just a negated or inverted output with glitches. I am expecting a chaotic or random output. Please help me what is the possible cause of this unsuitable output. Do I need to put a resistor-capacitor RC network between inverter stages just like a normal ring oscillator? Thanks in advance.