FIA Magnification of very small margins appears to be a problem

[loveviviforever]

Hi all, I am doing pipelined sar design with FIA structure as interstage margin amplifier. However, I found that the FIA amplification is very poor when my residual signal goes to μA stage, please what is the best idea to improve the FIA

 

[FvM]

I doubt that FIA is a commonly understood technical term, guess you are referring to floating inverter amplifier. Why not sketch the ADC topology, including a transistor level schematic of your FIA?

 

[loveviviforever]

I doubt that FIA is a commonly understood technical term, guess you are referring to floating inverter amplifier. Why not sketch the ADC topology, including a transistor level schematic of your FIA?

I built the ADC schematic and tested a two-stage FIA structure, which can achieve an open-loop gain of 46dB and a three-stage one of 78dB, but when I added it to my pipelined sar, the voltage change of the upper and lower pole plates of the front and rear stages gave me the feedback that it did not work

 

[dick_freebird]

Perhaps the problem with near-null current is in the time domain. You have stage internal C (Miller multiplied as the input sees it?) to slew with no juice to do it and clock's a-ticking?

You must at some point slide settling time past the metastability / setup time window. This may be error or test challenge depending on how you spec or measure: product test for high bit count ADCs has become statistical as practical noise floor is above LSB at any level of ATE hardware art (compatible with automated high speed test).