Dear,
Thank you for your response.
I am Using ISIM from Xilinx (ISE) as Modelsim is not working on my machine.
What is the input signal level?
Input Signal lelvel that I gave in Matalb is +/- 1 while I think we cannot give this in verilog.
Well my FFT is generated by Core generator
It has the following specs
Imaginary input = 0 (given by me)
Input bits 20
output (unscaled) 27
rest if bits are common lie
dv= valid data
done, edone, rfd etc
It is taking 64 pieces of data in 1 time.( what I think problem lies with this thing, coz
The Matlab code for generation of since wave is as follows
The following is the code for Matlab for genreating and storing sine wave binary into a file
later called by verilog simulation model
Code:
clc; clear all;close all;
%Sine wave of freqeuncy 200
f=200;
T=1/f;
Tmax=5*T;
dt=1/10000;
t=-Tmax:dt:Tmax;
fid2=fopen('binary.txt','w');
x=100*sin(2*pi*f*t);
plot(t,x);
%converting floaing point into fixed point
%with 20 bit word lentgth and 18 bit fraction length
y=fi(x,1,20,18);
%Converting fixed point into respective binary notation
z=bin(y);
%Writing binary strings into file 'binary.txt'
for i=1:length(x)
fprintf(fid2,'%s \r\n',z);
end
fclose(fid2);
my verilog simulation model is as under: NOTE: I have not included the regs and variable declarations
Code:
initial begin
$readmemb("binary.txt",mem); //taking Matlab data fro sine wave
mcd = $fopen("from_verilg.txt"); //Opening a FILE to wirite
end
always #5 clk = ~clk; //running clock
initial begin
// Initialize Inputs
ce = 1; start = 1; clk = 0; xn_re = 0;
fwd_inv = 1; unload = 1; fwd_inv_we = 1; xn_im = 0;
end
always@(posedge clk)
begin
if(rfd)
begin
if(i<=500) begin xn_re <= mem[i]; i <= i+1'b1; end
end
end
always@(negedge dv) if(i>= 500) $fclose(mcd);
//counting 501 sample of sine wave input from Matlab
always@(posedge clk)
if(dv) $fdisplay(mcd,"%b \n", xk_re);
The image that I draw from Matlab after getting the output from Verilog is as under
Bests and Many thanks
Shan
---------- Post added at 12:25 ---------- Previous post was at 12:25 ----------
Dear,
Thank you for your response.
I am Using ISIM from Xilinx (ISE) as Modelsim is not working on my machine.
What is the input signal level?
Input Signal lelvel that I gave in Matalb is +/- 1 while I think we cannot give this in verilog.
Well my FFT is generated by Core generator
It has the following specs
real input : xn_re from external file
Imaginary input = 0 (given by me)
Input bits 20
output (unscaled) 27
rest if bits are common lie
dv= valid data
done, edone, rfd etc
It is taking 64 pieces of data in 1 time.( what I think problem lies with this thing, coz
The Matlab code for generation of since wave is as follows
The following is the code for Matlab for genreating and storing sine wave binary into a file
later called by verilog simulation model
Code:
clc; clear all;close all;
%Sine wave of freqeuncy 200
f=200;
T=1/f;
Tmax=5*T;
dt=1/10000;
t=-Tmax:dt:Tmax;
fid2=fopen('binary.txt','w');
x=100*sin(2*pi*f*t);
plot(t,x);
%converting floaing point into fixed point
%with 20 bit word lentgth and 18 bit fraction length
y=fi(x,1,20,18);
%Converting fixed point into respective binary notation
z=bin(y);
%Writing binary strings into file 'binary.txt'
for i=1:length(x)
fprintf(fid2,'%s \r\n',z);
end
fclose(fid2);
my verilog simulation model is as under: NOTE: I have not included the regs and variable declarations
Code:
initial begin
$readmemb("binary.txt",mem); //taking Matlab data fro sine wave
mcd = $fopen("from_verilg.txt"); //Opening a FILE to wirite
end
always #5 clk = ~clk; //running clock
initial begin
// Initialize Inputs
ce = 1; start = 1; clk = 0; xn_re = 0;
fwd_inv = 1; unload = 1; fwd_inv_we = 1; xn_im = 0;
end
always@(posedge clk)
begin
if(rfd)
begin
if(i<=500) begin xn_re <= mem[i]; i <= i+1'b1; end
end
end
always@(negedge dv) if(i>= 500) $fclose(mcd);
//counting 501 sample of sine wave input from Matlab
always@(posedge clk)
if(dv) $fdisplay(mcd,"%b \n", xk_re);
The image that I draw from Matlab after getting the output from Verilog is as under
Bests and Many thanks
Shan