FFs/Latches (without init value) have a constant value of 0

[Nikolai]

warning:xst:2404

Im am getting the above warning in my design and the output is constantly 0;

The following is my code for a 'rotator' from DCT signal flow graph proposed by Loeffler. (Q7 data format)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Quad_multiplier_A1 is
Port ( IN1 : in STD_LOGIC_VECTOR (7 downto 0);
IN2 : in STD_LOGIC_VECTOR (7 downto 0);
OUT1 : out STD_LOGIC_VECTOR (7 downto 0);
OUT2 : out STD_LOGIC_VECTOR (7 downto 0);
OE : in STD_LOGIC);
end Quad_multiplier_A1;

architecture Behavioral of Quad_multiplier_A1 is

Signal Cn : std_logic_vector (7 downto 0) := "01111101"; -- 0.980
Signal Sn : std_logic_vector (7 downto 0):= "00011001"; -- 0.195

Signal Mul_result_1 : std_logic_vector (15 downto 0);
Signal Mul_result_2 : std_logic_vector (15 downto 0);
Signal Mul_result_3 : std_logic_vector (15 downto 0);
Signal Mul_result_4 : std_logic_vector (15 downto 0);
Signal Add_result_1 : std_logic_vector (7 downto 0) ;
Signal Add_result_2 : std_logic_vector (7 downto 0);

Signal Temp1 : std_logic_vector (15 downto 0); -- to store before left shifting once
Signal Temp2 : std_logic_vector (15 downto 0); -- ,,
Signal Temp3 : std_logic_vector (15 downto 0); -- ,,
Signal Temp4 : std_logic_vector (15 downto 0); -- ,,


Signal Temp5 : std_logic_vector (7 downto 0); -- to store before right shifting once
Signal Temp6 : std_logic_vector (7 downto 0); -- ,,

begin

Temp1 <= IN1 * Cn;
Temp2 <= IN2 * Sn;
Temp3 <= IN1 * Sn;
Temp4 <= IN2 * Cn;

Mul_result_1 <= Temp1 (14 downto 0) & '0';
Mul_result_2 <= Temp2 (14 downto 0) & '0';
Mul_result_3 <= Temp3 (14 downto 0) & '0'; -- left shifting multiplication result
Mul_result_4 <= Temp4 (14 downto 0) & '0';

Temp5 <= Mul_result_1 (15 downto 8) + Mul_result_2 (15 downto 8); -- adding MSB
Temp6 <= Mul_result_4 (15 downto 8) - Mul_result_3 (15 downto 8); -- discarding LSB

Add_result_1 <= '0' & Temp5 (7 downto 1);
Add_result_2 <= '0' & Temp6 (7 downto 1);


OUT1 <= Add_result_1 when (OE'event and OE = '1');
OUT2 <= Add_result_2 when (OE'event and OE = '1');

end Behavioral;

Now here's the synthesis report

Release 9.1i - xst J.30
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 1.44 s | Elapsed : 0.00 / 2.00 s

--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 1.45 s | Elapsed : 0.00 / 2.00 s

--> Reading design: Quad_multiplier_A1.prj

TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT


=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "Quad_multiplier_A1.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters
Output File Name : "Quad_multiplier_A1"
Output Format : NGC
Target Device : xc2s200-5-pq208

---- Source Options
Top Module Name : Quad_multiplier_A1
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : lut
Automatic Register Balancing : No

---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100
Add Generic Clock Buffer(BUFG) : 4
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Convert Tristates To Logic : Yes
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES

---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : Quad_multiplier_A1.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5

=========================================================================


=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/MyProjects/VHDL/Daedalus/Quad_multiplier_A1/Quad_multiplier_A1.vhd" in Library work.
Entity <quad_multiplier_a1> compiled.
Entity <quad_multiplier_a1> (Architecture <behavioral>) compiled.

=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <Quad_multiplier_A1> in library <work> (architecture <behavioral>).


=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <Quad_multiplier_A1> in library <work> (Architecture <behavioral>).
Entity <Quad_multiplier_A1> analyzed. Unit <Quad_multiplier_A1> generated.


=========================================================================
* HDL Synthesis *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <Quad_multiplier_A1>.
Related source file is "C:/MyProjects/VHDL/Daedalus/Quad_multiplier_A1/Quad_multiplier_A1.vhd".
WARNING:Xst:646 - Signal <Temp1<15>> is assigned but never used.
WARNING:Xst:646 - Signal <Temp2<15>> is assigned but never used.
WARNING:Xst:646 - Signal <Temp3<15>> is assigned but never used.
WARNING:Xst:646 - Signal <Temp4<15>> is assigned but never used.
WARNING:Xst:646 - Signal <Temp5<0>> is assigned but never used.
WARNING:Xst:646 - Signal <Temp6<0>> is assigned but never used.
WARNING:Xst:653 - Signal <Cn> is used but never assigned. Tied to value 01111101.
WARNING:Xst:646 - Signal <Mul_result_1<7:0>> is assigned but never used.
WARNING:Xst:646 - Signal <Mul_result_2<7:0>> is assigned but never used.
WARNING:Xst:646 - Signal <Mul_result_3<7:0>> is assigned but never used.
WARNING:Xst:646 - Signal <Mul_result_4<7:0>> is assigned but never used.
WARNING:Xst:653 - Signal <Sn> is used but never assigned. Tied to value 00011001.
WARNING:Xst - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst - Property "use_dsp48" is not applicable for this technology.
Found 8-bit register for signal <OUT1>.
Found 8-bit register for signal <OUT2>.
Found 8x8-bit multiplier for signal <Temp1>.
Found 8x8-bit multiplier for signal <Temp2>.
Found 8x8-bit multiplier for signal <Temp3>.
Found 8x8-bit multiplier for signal <Temp4>.
Found 8-bit adder for signal <Temp5>.
Found 8-bit subtractor for signal <Temp6>.
Summary:
inferred 16 D-type flip-flop(s).
inferred 2 Adder/Subtractor(s).
inferred 4 Multiplier(s).
Unit <Quad_multiplier_A1> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Multipliers : 4
8x8-bit multiplier : 4
# Adders/Subtractors : 2
8-bit adder : 1
8-bit subtractor : 1
# Registers : 2
8-bit register : 2

=========================================================================

=========================================================================
* Advanced HDL Synthesis *
=========================================================================

Loading device for application Rf_Device from file 'v200.nph' in environment C:\Xilinx91i.
WARNING:Xst:2404 - FFs/Latches <OUT1<7:7>> (without init value) have a constant value of 0 in block <Quad_multiplier_A1>.
WARNING:Xst:2404 - FFs/Latches <OUT2<7:7>> (without init value) have a constant value of 0 in block <Quad_multiplier_A1>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Multipliers : 4
8x8-bit multiplier : 4
# Adders/Subtractors : 2
8-bit adder : 1
8-bit subtractor : 1
# Registers : 14
Flip-Flops : 14

=========================================================================

=========================================================================
* Low Level Synthesis *
=========================================================================

Optimizing unit <Quad_multiplier_A1> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block Quad_multiplier_A1, actual ratio is 4.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers : 14
Flip-Flops : 14

=========================================================================

=========================================================================
* Partition Report *
=========================================================================

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : Quad_multiplier_A1.ngr
Top Level Output File Name : Quad_multiplier_A1
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO

Design Statistics
# IOs : 33

Cell Usage :
# BELS : 502
# GND : 1
# INV : 32
# LUT1 : 30
# LUT2 : 114
# MUXCY : 174
# VCC : 1
# XORCY : 150
# FlipFlops/Latches : 14
# FD : 14
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 32
# IBUF : 16
# OBUF : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200pq208-5

Number of Slices: 102 out of 2352 4%
Number of 4 input LUTs: 176 out of 4704 3%
Number of IOs: 33
Number of bonded IOBs: 33 out of 140 23%
IOB Flip Flops: 14
Number of GCLKs: 1 out of 4 25%

---------------------------
Partition Resource Summary:
---------------------------

No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
OE | BUFGP | 14 |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found
Minimum input arrival time before clock: 17.208ns
Maximum output required time after clock: 7.999ns
Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'OE'
Total number of paths / destination ports: 97002 / 14
-------------------------------------------------------------------------
Offset: 17.208ns (Levels of Logic = 17)
Source: IN1<7> (PAD)
Destination: OUT1_6 (FF)
Destination Clock: OE rising

Data Path: IN1<7> to OUT1_6
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 5 0.924 1.740 IN1_7_IBUF (IN1_7_IBUF)
INV:I->O 2 0.653 1.340 IN1<7>_inv1_INV_0 (IN1<7>_inv)
LUT2:I1->O 1 0.653 0.000 Mmult_Temp1_Madd_lut<4> (N32)
MUXCY:S->O 1 0.784 0.000 Mmult_Temp1_Madd_cy<4> (Mmult_Temp1_Madd_cy<4>)
MUXCY:CI->O 1 0.050 0.000 Mmult_Temp1_Madd_cy<5> (Mmult_Temp1_Madd_cy<5>)
MUXCY:CI->O 1 0.050 0.000 Mmult_Temp1_Madd_cy<6> (Mmult_Temp1_Madd_cy<6>)
XORCY:CI->O 4 0.500 1.600 Mmult_Temp1_Madd_xor<7> (Mmult_Temp1_Madd_10)
LUT2:I1->O 1 0.653 0.000 Mmult_Temp1_Madd4_lut<10> (N84)
MUXCY:S->O 1 0.784 0.000 Mmult_Temp1_Madd4_cy<10> (Mmult_Temp1_Madd4_cy<10>)
MUXCY:CI->O 1 0.050 0.000 Mmult_Temp1_Madd4_cy<11> (Mmult_Temp1_Madd4_cy<11>)
XORCY:CI->O 1 0.500 1.150 Mmult_Temp1_Madd4_xor<12> (Mmult_Temp1_Madd_124)
LUT2:I1->O 1 0.653 0.000 Mmult_Temp1_Madd5_lut<12> (N128)
MUXCY:S->O 1 0.784 0.000 Mmult_Temp1_Madd5_cy<12> (Mmult_Temp1_Madd5_cy<12>)
XORCY:CI->O 1 0.500 1.150 Mmult_Temp1_Madd5_xor<13> (Temp1<13>)
LUT2:I0->O 1 0.653 0.000 Madd_Temp5_lut<6> (N149)
MUXCY:S->O 0 0.784 0.000 Madd_Temp5_cy<6> (Madd_Temp5_cy<6>)
XORCY:CI->O 1 0.500 0.000 Madd_Temp5_xor<7> (Temp5<7>)
FD 0.753 OUT1_6
----------------------------------------
Total 17.208ns (10.228ns logic, 6.980ns route)
(59.4% logic, 40.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'OE'
Total number of paths / destination ports: 14 / 14
-------------------------------------------------------------------------
Offset: 7.999ns (Levels of Logic = 1)
Source: OUT1_6 (FF)
Destination: OUT1<6> (PAD)
Source Clock: OE rising

Data Path: OUT1_6 to OUT1<6>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 1 1.292 1.150 OUT1_6 (OUT1_6)
OBUF:I->O 5.557 OUT1_6_OBUF (OUT1<6>)
----------------------------------------
Total 7.999ns (6.849ns logic, 1.150ns route)
(85.6% logic, 14.4% route)

=========================================================================
CPU : 9.31 / 10.86 s | Elapsed : 9.00 / 11.00 s

-->

Total memory usage is 129724 kilobytes

Number of errors : 0 ( 0 filtered)
Number of warnings : 16 ( 0 filtered)
Number of infos : 0 ( 0 filtered)


Now i dont understand the warning in the Advanced HDL synthesis. N so even my output is wrong.

Any ideas ?

 

[nxtech]

(without init value)has a constant value

From looking at your code it does not look like you are shifting left properly. Your codes places a zero on the right hand side. This implies that you will always have a 0 on the right hand side when you cannot.

Hand work your code on paper to make sure things are as they should be and remember, just because it works on paper does not mean that it will synthesize properly.

E

 

[FvM]

xst:2404

Hello,

I apologize not being able to analyze your code in detail, but I see two issues
1. the conditional assignment with an event condition (= rising_edge()) isn't a defined VHDL construct to my opinion, particularly it doesn't instatiate a flip-flop or latch. I'm not even sure, if the result with different compilers can be predicted. If a clock synchronous flip-flop is intended, a process must be used. The signal name OE suggests a tristate output, but this would need a different construct:

OUT1 <= Add_result_1 when OE = '1' 
    else 'Z';

2. The final bitshift may have a different result than intended. I understand, that a scaling is performed, probably like a vector rotation. In this case, the 8 leftmost bits would represent the result, dropping the 8 lower bits. You should try with numerical examples. The correct scaling of fixed-point multiplication is always a bit difficult to my opinion.

If the uppermost bits are dropped, as in the posted code, overflow would occur for most of the possible input range. Sometimes a rightshifted multiply may be intended as a kind of "amplification", but then saturation logic would be useful.

If multiplications is used repeatedly in a design, a function can ease your work a lot. As an example, see my signed multiply function (it has an additional shift by one for the sign bit with)

FUNCTION MUL(X1,X2: SIGNED) RETURN SIGNED IS
-- Simple multiply, result length equals X2 length
VARIABLE P:SIGNED(X1'length+X2'length-1 downto 0);
  BEGIN
    P:=X1*X2;
    RETURN P(P'left-1 downto X1'length-1);
  END;

More elaborated versions also perform saturation in case of overflow or additional shift to scale output.

Regards,
Frank

P.S.: I did yet think in special about the warning in thread title

FFs/Latches (without init value) have a constant value of 0

I think, the only latch in the design (may be unintended) is related to the discussed issue 1. Unfortunately, I don't know how the XILINX ISE interprets this construct. With Altera Quartus synthesis, it is simply ignored, which is probably the best thing, a HDL compiler can do. Apparently XILINX infers a latch here. But I don't see, if the output is 0, cause the latch never has an active latch command (issue 1) or cause the input is constantly 0 (issue 2 or a different problem).

 

[Nikolai]

signal <temp2> is assigned but never used xst

Ok, here's a slightly detailed explanation of my code.

@Nxtech

Two 8-bit Q7 number multiplication results in 16-bit Q15 number. Now im getting rid of the extended sign bit first by left shifting once.

Then im adding the MSB (15 to 8) of the resulting numbers. And finally im scaling the result by 2 (right shifting once) to ensure that overflow doesnt occur after addition.

So i dont see any problem in shifting.

@FvM

the attached diagram will probably give you a better idea of my intentions.

The Latch/FF is intentional.

Im using Xilinx ISE 9.1.

OUT1 <= Add_result_1 when (OE'event and OE = '1'); -- is synthesized as a FF.

while

OUT1 <= Add_result_1 when OE = '1'; -- is synthesized as a Latch.

Now the warning does appear even when it is synthesized as a latch, but the code works as expected. The problem comes only when it is synthesized as a FF.

I want a Latch/FF over there since i want the O/P to remain stable for the next stage, while the rotator performs over next set of inputs. Thus i cannot include the
" else 'Z' " clause in the WHEN statement.

 

[FvM]

a constant value is expected

Hello,

don't need to argue regarding the correct scaling of the multiply. It should have a result anyway, and you'll see the result. May be I missunderstood the intention and it's coded as intended, if not, you can correct it later.

I clearly understand the purpose of holding the output. But it isn't coded this way. You can consult any VHDL textbook, how a FF could be coded to be understood by any tool.

The way you write the code, it is effectively a hidden sequential statement. This seems to work with an ansynchronous latch, but not with synchronous FF.

The usual syntax, that should work with any tool is

process (OE)
begin
-- a shortcut  for OE'event and OE = '1'
  if rising_edge(OE) then 
    begin
      OUT1 <= Add_result_1;
      OUT2 <= Add_result_2;
    end;
end process;

The sequential block can be placed anywhere in concurrent statement part. You may add a reset signal to your design and a asynchronous reset condition to the FF, I regard it as good engineering practice, but it isn't absolutely necessary.

  if RESET = '1' then
    OUT1 <= (others => '0');
    OUT2 <= (others => '0');
  elsif rising_edge(OE) then 
    begin
      OUT1 <= Add_result_1;
      OUT2 <= Add_result_2;
    end;

Personally, I wouldn't use the designator OE for a synchronous clock, but that's less important.

Regards,
Frank

 

[Nikolai]

muxcy in altera

@ FvM

I have tried using both the codes that u posted in the previous post.
But the problem persists.

Im attaching the RTL schematic. Wats strange is output OUT2 is nowhere to be found.
But the technology schematic is proper.

actually OE was supposed to function like an Output Enable. XST inferred it as a clock signal and assigned it a global clock line. Even i have no intentions of using it as a clock.

 

[FvM]

has a constant value of 0

Hello,

to make me understand the origin of the strange RTL map you posted, can you send code where it was generated from as an attachment? I don't have Xilinx tools installed, but if the code is correct, it should compile with ModelSim or Quartus integrated synthesis as well. If not, one should get at least a warning. But outputs tied to GND normally have a simple reason.

Regarding the OE/clock question: When OE rising edge latches the outputs, OE is effectively a clock, also an asynchronous latch control signal would be regarded as clock in timing analysis and other aspects. If it's routed through global clock resources or locally has some impact on timing, but makes no basic difference. This is can be decided by the compiler.

A basic question is regarding the clock scheme used in your design. Typically you'll have a global clock for your design or a design partition, that is used for all (or nearly all) synchronous action within. If so, your "OE" could be identical with this global clock, creating a pipeline of multiply blocks. Or you may want the output to be updated conditional. Then, the block should have CLK and OE as inputs. CLK would be the synchronous clock, and OE an additional clock enable.

process (CLK)
begin
if rising_edge(CLK) and OE='1' then
begin
OUT1 <= Add_result_1;
OUT2 <= Add_result_2;
end;
end process;

Regards,
Frank

 

[Nikolai]

synthesis input constaint latch

Im attaching the code and its testbench.

My design can be summarised as follows. It consists of 4 stages , each having adders,multipliers,etc. The output of each stage is controlled by an OE signal. Ie each component in the stage will have an OE associated with it. Now the OE signal is provided to the stages by an FSM (control unit). So the global clock signal will be given only to the FSM and the FSM will in turn generate the necessary OE signals...

Hope this helps..

 

[FvM]

global optimization ise

Hello,

I'll check the code. The testbench don't work this way, cause OE is set to '1' simultanously with applying the input. You should move the first delay.

wait for 50 ns;
IN1 <= "01100000";
IN2 <= "00100000";
-- need a wait before OE rising edge!
OE <= '1';
wait for 10 ns;
OE <= '0';
wait for 100 ns;
-- Place stimulus here
wait; -- will wait forever

Regards,
Frank

 

[Nikolai]

xst 2404

By duke's nose !!! It actually worked. I simply put a delay before the OE = '1' and the output is fine.

Now only the strange RTL needs to be explained.

 

[FvM]

ise has a constant valueo of

Hello,

it's operating in my test. I append the result for your testvector, I only added a reset stimulus and delayed the OE as discussed. Couldn't hardly imagine that Xilinx sees something different.

However, the compiler says, that OUTx[7] are stuck to GND. That's a result of the applied scaling, I think, you should know better. Also, the constants could be written as such, CONSTANT Sn instead of SIGNAL Sn, the compiler issues a warning about the signal using only default value, but that's o.k.

You have been generally right regarding the multiply result shift. I did overlook the line with [15 downto 8] subrange selection. Sorry for the confusion.

I'm visiting friends shortly, coming back some hours later.

Regards,
Frank

 

[Nikolai]

device utilization

Yes i failed to notice OUT1<7:7> which means the 7th bit is tied to GND which is obvious for the right shift.

Also i changed Sn and Cn to CONSTANT. Alls working fine now.

Except for the RTL. Probably its an ISE bug ? Since the technology schematic is al expected.

Neway, all thanks !

 

[vipinlal]

here is your solution..
https://vhdlguru.blogspot.com/2010/03/synthesis-warning-fflatch-has-constant.html