Few questions regarding different subjects

[AMSA84]

Hi all,

I am trying to get a feedback specially from those who are in the industry and have some privileged obtained through the years, regarding some questions that came up to me when I was designing a dc-dc converter. Of course there are others that anyone else might know. There is no especial order.

What kind of circuit/amplifier topology/techniques with some circuit, can allow a very high GBW? For example, near 1GHz?

It is possible to implement some sort of circuit that allows a bandgap circuit not change its output voltage when the power supply of the all circut varies? Like a line variation. How? References?

There is any way to compensate or anulate the frequency change on a sawtooth generator when the power supply voltage changes? That is, make the sawtooth generator as much as possible insensible to power supply change?

How the design of a moscap should be made to minimize as possible the ESR value?

Why the positive feedback of a cross-couple comparator has a value of -1/gm? How to get there?



Is there any tool in the cadence layout design tool (Layout XL) that can allow the introduction of slots in the a very wide metal, for example 50um (it does not comply with DRC rules, so we must insert slots right?)?

If I remember one or two more I will post it here! (I have forgotten)

Thank you for your attention.

Kind regards.

 

[dick_freebird]

You can make a very supply insensitive bandgap by placing it
under local regulation - an internal LDO. Even a crude one can
be very effective, it doesn't need good tempco itself (bandgap
can take that out), only to cut supply swing from 10% to <1%
and this is pretty doable (have done, good results).

A supply insensitive ramp is not as easy but if you wanted to
use a RC triangle wave as your timing waveform, that is pretty
supply independent (if you use supply-ratiometric top and
bottom thresholds, and comparators fast enough). You also
would get a less noisy circuit without the hard-banging
discharge.

MOSCAPs should be fingered, oversquare (W >> L).

I have seen PDKs that have stuff like "M1_slot" which can
be drawn as a polygon where you want it, and then use a
DRC script to andNot this with the companion main metal
layer to produce a slotted final layer. In the past I used to
have groundrules-prescribed ortho and diagonal oriented
slot templates which I would drag around and then poly-cut
the slots using these, move them, repeat. Crude, but it
got the job done.

In the context of power supplies I have nothing to recommend
for a 1GHz UGBW amplifier, including applications. Nobody sane
runs over a couple of MHz chop rate and the error amp doesn't
have to be more than 100X better before its gain error has no
significance to transient following. More likely you'll kill its BW
on purpose to stabilize the loop.

 

[AMSA84]

freebird, I'll answer you shortly.

Another question that I remembered.

When designing a driver chain, to drive a power mosfet, using the methodology os tapering factor and so on, we start from the power mosfet and then we go backwards.

Well. For example, if I have a power mosfet with 1000um and a tap factor of 3, it means that we divide the power mosfet by 3 and we get 334um.

Then this value is THE TOTAL area of the driver inverter type (of both transistors) or it is for the PMOS only, for example? If it is from the PMOS, then I would divide by 3 again (doesn't have nothing to do with the tapering favtor. This divide by 3 is to mantain that thing of the mobility un and up etc).
If it is the TOTAL are then, taking into account that the magical number is 3 to mantain that mobility thing, then the pmos of the driver based on the inverter will have more area.

Which one is the practice?

 

[AMSA84]

Hi freebird, thank you for your input.

Regarding your answer about the slots: I will check that in my PDK. However, allow me to ask you another thing. I will try to explain with an example so that you can understand what I mean.

Imagine you must design a metal with a width of 100um. Of course it does not comply with the DRC. The PDK allows up 10um, no slot needed. Up to 25um it must be slotted. Up to 100um it is impossible because the foundry does not allow metal widths > 25um.

Now to design the 100um metal track width what's the basic approach? My thoughts:

1st: 4 x 25um with the minimum allowed space by the DRC, connected to each other through perpendicular metal?
2nd: 1 big 100um all slotted in a way that complies with the DRC rules?

---

About the amplifier: Maybe I didn't explain myself correctly. What I meant to say is that what amplifier/technique/etc is suitable to extend the bandwidth of the amplifier so that he doesn't limit the required compensation network shape? Did you followed?

---

MOSCAP: So what you mean (my interpretation) is that I should use a small cell (transistor connected as a capacitor) with a rectangular shape (multifingered)? It outperforms better when compared for example to a small cell with a square shape (multiifred)?

---

With respect to the sawtooth generator: Here there is not much to do then? It will allways be supply dependent?

Thank you in advance for you availability! Kind regards.

- - - Updated - - -

freebird, I remembered another thing, regarding the sawtooth generator.

What if one use an LDO, the same one that is used for the bandgap, to regulate the power supply voltage of sawtooth generator generator block?