[SOLVED] FET transistors

[Mabrok]

For FET transistors, drain and source pin should be connected when check continuity using multi meter or no?

 

[danadakk]

For some small signal JFETS do not forward bias the G-S or G-D junction, as that
may degrade noise performance of JFET. That problem has been observed in small
signal RF jfets.

Note some circuit design uses JFET as a diode with gate one lead and S-D connected together
for the other lead.

https://www.edn.com/simple-circuit-lets-you-characterize-jfets/

Regards, Dana.

 

[KlausST]

Hi?

What do you want to achieve?
What do you expect?

Generally the Fet's D-S resistance depends on G-S voltage. But G-S is that high impedance that there may exist unknown voltage (due to capacitance and leakage currents). Unknown voltage results in unknown D-S behaviour.


Klaus

 

[Mabrok]

Hi?

What do you want to achieve?
What do you expect?

Generally the Fet's D-S resistance depends on G-S voltage. But G-S is that high impedance that there may exist unknown voltage (due to capacitance and leakage currents). Unknown voltage results in unknown D-S behaviour.


Klaus

Hi. Thanks for your reply. Want to connect dc power supply to bias common source amplifier. When connect dc power supplies at drain and gate terminals and switch on the dc power supply. The drain side short to the ground.

 

[KlausST]

Hi,

Still no clear information. It makes it impossible to give good assistance.
-> Use a pen and a sheet of paper and draw what you want to achieve.

There are thousands of hits if you do an internet search on "how to design a common source FET amplifier".
Read through some of them. Choose one that fits you best.Post the link to the document and ask what is unclear.

Klaus

 

[Mabrok]

Hi,

Still no clear information. It makes it impossible to give good assistance.
-> Use a pen and a sheet of paper and draw what you want to achieve.

There are thousands of hits if you do an internet search on "how to design a common source FET amplifier".
Read through some of them. Choose one that fits you best.Post the link to the document and ask what is unclear.

Klaus

After i connect dc sources at drain and terminal sides and switch on dc source. I got short at drain side. So how to properly connnect dc source at drain and gate? VDS 28 V, VGS -3.2
Thank you

 

[FvM]

The question has been already answered in your cross posted thread https://www.edaboard.com/threads/cgh40010f-transistor-provided-by-cree-company.394170/

Your transistor is a depletion mode transistor (normally on).

 

[Mabrok]

What does it mean by normally on?
Why when switch on power supplies, it shorted

 

[FvM]

There are two possiblities:
- You didn't apply a negative bias to the gate, as required for this transistor type, see the explanations in your other thread.
- You see a high drain current despite of a negative bias. Then you have probally killed the FET.

 

[betwixt]

Depletion mode means it conducts between drain and source until you turn it off.
Enhancement mode means it normally doesn't conduct until you turn it on.

By conduction I mean between the source and drain pins. Turning a depletion mode FET off usually means a voltage between the gate and source that is the opposite polarity as the voltage from drain to source has to be applied. Turning an enhancement mode FET on usually means applying a gate voltage with respect to the source that is the same polarity as the drain voltage.


Brian.

 

[Mabrok]

There are two possiblities:
- You didn't apply a negative bias to the gate, as required for this transistor type, see the explanations in your other thread.
- You see a high drain current despite of a negative bias. Then you have probally killed the FET.

For the first possibility, i am sure that applied negative voltage at gate side with -3.2 V.
The second possibility i did not understand well( i applied 28 V at drain side) the current in this case for 28 V at drain with -3.2 V at gate side is IDS= 13 mA

 

[FvM]

the current in this case for 28 V at drain with -3.2 V at gate side is IDS= 13 mA

So when do you see it shorted?

 

[Mabrok]

So when do you see it shorted?

The current observed during simulation. Not measurements. For shorting, once switch on power supplies, it shorted directly at drain side. I have tested the transistor for damaging by measuring gate resistance as recomended by manufactuerer, and got it not damaged.

--- Updated Aug 6, 2020 ---

Is that correct, connected dc power supplies at drain and gate sides. And switch them on at the same time. Or need to connect dc to gate side first, then drain side later? Are there any specfic order

 

[FvM]

Power supply sequence has been addressed in your other thread. Surely gate bias first.

The current observed during simulation. Not measurements.

Doesn't make much sense, probably wrong simulation setup. Can't assess without seeing the simulation.

 

[Mabrok]

Power supply sequence has been addressed in your other thread. Surely gate bias first.
Doesn't make much sense, probably wrong simulation setup. Can't assess without seeing the simulation.

Just for confirmation, need to connect power supply at gate side first and switch on. Then, while the voltage is switched on at gate side, i connect the dc at drain side. Am I right?

 

[FvM]

Yes exactly

 

[Mabrok]

Yes exactly

Thanks for the confirmation. Not following this sequence can cause short circuit (drain to ground)?

 

[dick_freebird]

You should distinguish between "short circuit"
(which does not respond to Vgs) and "low on-
resistance" / "high drain current" (which does
respond to Vgs, if only you followed the norms
of application).

Element control circuits for such devices often
include a drain switch whose action is inhibited
if Vgs is not at a reasonable negative potential.

Here's a thing to try. Ground the gate, put (say)
100 ohms series power resistor from source to
ground and apply drain voltage (+28V, or less
but no less than 12V). Measure the source voltage
at the top of that resistor. If it's about 3V then the
FET (HEMT) is roughly right. Much higher (like >10V)
and you may have a real short. You might also
put the G=Gnd connection through an ammeter
to assess gate integrity at the same time.

You don't need a lot of equipment, if you have
a proper idea of how the device is supposed to
work.

 

[Mabrok]

Power supply sequence has been addressed in your other thread. Surely gate bias first.
Doesn't make much sense, probably wrong simulation setup. Can't assess without seeing the simulation.

During the measurements, i got high current 930 mA from dc power supply at the drain side (at the same time voltage at drain side dropped from 28 V to oV), as in the transistor datasheet the current suppose to be 200 mA. What does it mean?

 

[FvM]

According to a previous statement, the "measurement" refers to a simulation. But we don't know the actual simulation setup.