Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

feed forward compensated adpll

Status
Not open for further replies.
T

tv123

Junior Member level 3
Junior Member level 3
Joined
Mar 16, 2015
Messages
27
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
162
i am working on fast locking adpll via feed forward compensation. I have coded 5 blocks but not able to code LC block and combine with the architecture. anybody pls help. I have attached a paper.

Also pls suggest whether i have to combine blocks in verilog structural level or using state dgm(fig2 of paperView attachment BASE PAPER.pdf)
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top