Fault coverage in RTL code

[aditya_vij]

i have design BIST multiplier .
to calculate fautl coverage of above chip . i have to induce fault in intermediate nodes.
can any one know how to induce fault in RTL desing .

 

[dr_dft]

To inject a single fault in Verilog, you can simply use the 'force' statement.
However, it is not a common practice to find fault coverage in RTL. The reason is that the fault coverage number may vary significantly with implementation. That is why there are only fault coverage 'estimators' in RTL, but no 'calculators'.

 

[AlexWan]

Hi, aditya_vij

Why do you plan to test stuck-at fault in RTL phase? After synthesis and P&R, the wire name and the latch name will change. You can't ensure the fault coverage in RTL phase is equal in the Netlist phase.