eng.msmahmoud
Newbie level 5

Dear all
i am a new to VHDL and i have to questions
1- iam using model sim students edition to compile the following code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY latch IS
PORT( d,clk: IN bit;
q,nq : OUT bit);
END ENTITY latch ;
ARCHITECTURE behav OF latch IS
BEGIN
p1 : PROCESS (d,clk) IS
BEGIN
IF CLK = '1' THEN
q<=d; nq<= NOT(d);
END IF ;
END PROCESS p1 ;
END ARCHITECTURE behav ;
the compilation pass successful and when i tried to simulate the following errors appears
# ** Fatal: (vsim-3369) Top-level design unit 'latch' specified more than once.
# Time: 0 ns Iteration: 0 Root: / File: NOFILE
# FATAL ERROR while loading design
# Error loading design
Second question
why should i use xinix or altera tools to compile my code and link them to modelsim instead of compiling and simulating on modelsim
Thanks
i am a new to VHDL and i have to questions
1- iam using model sim students edition to compile the following code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY latch IS
PORT( d,clk: IN bit;
q,nq : OUT bit);
END ENTITY latch ;
ARCHITECTURE behav OF latch IS
BEGIN
p1 : PROCESS (d,clk) IS
BEGIN
IF CLK = '1' THEN
q<=d; nq<= NOT(d);
END IF ;
END PROCESS p1 ;
END ARCHITECTURE behav ;
the compilation pass successful and when i tried to simulate the following errors appears
# ** Fatal: (vsim-3369) Top-level design unit 'latch' specified more than once.
# Time: 0 ns Iteration: 0 Root: / File: NOFILE
# FATAL ERROR while loading design
# Error loading design
Second question
why should i use xinix or altera tools to compile my code and link them to modelsim instead of compiling and simulating on modelsim
Thanks