Fatal error in vhdl. - Failed to open VHDL file "sample

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satheeshkumars

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sample_int.yuv

hello
I am writing a vhdl program for h264 video compression transformation and quantization and i run it in modelsim but it gives me the following error

** Error: (vsim-7) Failed to open VHDL file "sample_int.yuv" in rb mode.
# No such file or directory. (errno = ENOENT)


why? plz help me out....
 

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