[SOLVED] Faster PMOS turn-off time

[kathmandu]

Hello friends, I want to invert the output of an optocoupler using a PMOS transistor. Anyway, I've got an unacceptable long (400ns) turn-off time.
I'm using a 1kohm pull-up resistor at optocoupler output (thus between PMOS gate and source). Is there any circuit (like BJT baker clamp os speed-up capacitor) to enhance the turn-off?

 

[crutschow]

Use a lower resistor or a BJT driver for the gate.
Post your schematic.

 

[dick_freebird]

If you don't have access to the optocoupler base then
a Baker or Schottky clamp can't do anything for you.
You might want to determine whether the turnoff is due
to internal saturation of the opto, to the simple gate RC
and distance-to-fall of the PMOS gate load, etc. and
maybe that will guide you. Sizing the PMOS, using a small
signal fast PNP instead, or using a CMOS inverter (Schmitt)
are options. There are some small sized PMOS from ALD
which could be faster for you than a single larger one as
most discretes are. How much load current is needed,
you did not say - nor desired supply and signal levels.

 

[kathmandu]

Thank you for all your comments! The optocoupler is working fine (I got almost straight rise/fall edges at its output).
I'm using a low power/high speed PMOS (Microchip VP2106N3-G and it will drive a power mosfet driver input (TC4420) so the output curent requirement are very low. I'll try to recheck the PCB for any parasitic capacitance across GS (or GD).
I'll try to further reduce the pull-up resistor of the optocoupler (6N137) too (though I guess 470 ohm is the minimum allowed).

 

[kathmandu]

I've already tried a BJT with a baker clamp circuit (three schottky diodes) and a speed-up capacitor across base resistor with no better results. I already have the PCB thus a CMOS gate IC is out of question for now (but it supposed to be the better choice I agree).
I'll try to reduce the pull-up resistor to 360 ohm (330 ohm is the minimum allowed by the datasheet). Thanks everyone for your kind support.

 

[FvM]

If you want faster edges than 400 ns, you must not drive the PMOS transistor gate from a optocoupler with open collector output. Instead use either a fast BJT circuit or better a fast CMOS logic gate.

- - - Updated - - -

You didn't tell what the final output load is, but the main problem is the large PMOS capacitance. Using a smaller area transistor might help.

 

[kathmandu]

I did mention earlier that the PMOS will drive the input of a TC4420 (6A power MOSFET driver) thus the PMOS output current it's rather small (1mA). The PMOS transistor has the same supply voltage as the optocoupler (5V).
The PMOS input capacitance is around 50pF (datasheet) thus I still believe it's something parasitic involved.

 

[FvM]

I did mention earlier that the PMOS will drive the input of a TC4420.

Yes you did, overlooked it.
I think possible options (besides logic gate) are:
- use TC4429 instead of TC4420
- PMOSFET with lower capacitance
- BJT inverter stage

 

[kathmandu]

I've tried BJT first (see the above post) with no luck.
TC4429 isn't safe either (if the input is accidentally disconnected, the output goes high).
I think I'll go with logic gates. Btw, as I'm going to use a six inverter gates IC (CD7414), it's better to put all 6 inverter gates in parallel or just use one gate and connect the rest (inputs) to GND?

 

[mtwieg]

When you say turn-off time, are you referring to the rise/fall time of the PMOS drain, or to the total propagation delay from the input of the optocoupler to the PMOS drain? I'm thinking it must be the latter.

In any case, if you just want to invert a 5V logic signal, then there's no reason to not use a simple logic gate.

 

[kathmandu]

By "turn-off time" I meant the falling edge of the signal. After the optocoupler, it is almost vertical (50ns or so). At the PMOS (or PNP bjt) drain it's an almost perfect diagonal (400ns).

I hope the Mosfet driver inputs (TC4420) have schmitt triggers, to avoid false (re)triggering.

I didn't use inverter gates at first because I only needed one inverter gate and they only came in a pack of six (CD7414). Moreover, I never thought it could be so hard to get a fast switching inverter stage using a transistor.

 

[mtwieg]

By "turn-off time" I meant the falling edge of the signal. After the optocoupler, it is almost vertical (50ns or so). At the PMOS (or PNP bjt) drain it's an almost perfect diagonal (400ns).

Well the fall time of the PMOS drain voltage is more related to the rise time of the optocoupler output, not it's fall time (since it's an inverting circuit). The fall time of the PMOS drain will also depend on the drain pulldown resistor, which you haven't described yet. You mentioned before that its drain current is 1ma, which implies that pulldown resistor is 5K, which would explain the slow fall time by itself.

Moreover, I never thought it could be so hard to get a fast switching inverter stage using a transistor.

It shouldn't be hard, which is why I suspect something is getting lost in communication...

 

[kathmandu]

The optocoupler output it's an open collector hence it doesn't count at all for turning off the PMOS. The only component involved in this process it's the optocoupler pull-up resistor (and the PMOS gate capacitance).

The PMOS pull-down resistor is just for setting up the drain current (ON state).

Any usual Mosfet driver has sink current capabilities hence it could turn-off faster the driving Mosfet.

 

[mtwieg]

The optocoupler output it's an open collector hence it doesn't count at all for turning off the PMOS.

The output capacitance of the optocoupler will definitely have an impact.

The only component involved in this process it's the optocoupler pull-up resistor (and the PMOS gate capacitance).

The PMOS pull-down resistor is just for setting up the drain current (ON state).

Not quite. Even if the PMOS turns off instantly (Ids goes to zero), its drain voltage will not fall instantly due to its output capacitance Coss and the pull down resistance. This is why we must be careful when describing circuit operation. Turn off delay time and fall time are two completely different things (for a simple pulse there are six total timing parameters, as shown in your PMOS's datasheet). Fall time will depend on the drain pull down resistor, turn off delay time will depend on the gate pull up resistor.

 

[kathmandu]

Many thanks for your comprehensive explanations. Looks like I was on a wrong track.

It's not the delay I was aware of but the fall time. I could compensate the delay by modifying the deadtime but that "diagonal" falling edge could lead to false (re)triggering of the Mosfet driver circuit.

Ok then, I'll try to increase the drain current (by reducing the pull-down resistor). I thought it doesn't need such a large current as the Mosfet driver input requirements are very low.

Thank you very much for your time.

 

[mtwieg]

Right, the PMOS has an open drain output, much like the opto's open collector output. Both have transition times depending on the load resistance and node capacitance. I'm still surprised using a PNP BJT like a 2n3906 wouldn't help though.

Depending on what sort of power circuit you are ultimately driving, you should consider how the overall gate drive chain distorts your pulses. If its a circuit where cross conduction can occur, you must ensure that the distortion does not lead to cross conduction.

 

[kathmandu]

I'm still surprised using a PNP BJT like a 2n3906 wouldn't help though.

I share your feelings... more than that, I've got almost the same result using 2n3906 with a baker clamp & speed-up capacitor or that pmos.

Maybe I should have tuned those circuits a bit but I was running out of time so I went further.

Depending on what sort of power circuit you are ultimately driving, you should consider how the overall gate drive chain distorts your pulses. If its a circuit where cross conduction can occur, you must ensure that the distortion does not lead to cross conduction.

I'm checking the waveforms with an oscilloscope thus I won't risk to drive the full bridge with a bad signal. Anyway, except that "diagonal" falling edge, the signals are absolutely clean. Btw, the rising edge is almost perfect.

I have chosen a deadtime of 600ns but after adding the above inverter stage I only got ~200ns of clean deadtime. That's why I have increased the deadtime to 900ns for now to test the full bridge stage.

I'm going to follow your advice and change the pull-down resistor before I make a different PCB with logic gates as inverters.

 

[kathmandu]

In the name of science, I've just came to make mea culpa: actually, I was making the measurements without a pull-down resistor!

That is, the pull-down resistor was placed on a separate board (at the input of TC4420 Mosfet driver) thus when I disconnected the boards to place the oscilloscope probe the pull-down resistor was gone.

With a pull-down resistor of 360 ohm I got a fall time under 100 ns (that's a good result, taking account of the improper PCB layout made for the bjt and its baker clamp circuit).

Thanks everybody for the valuable help.

 

[mrinalmani]

I see from the datasheet of your P-MOS that the reverse recovery time of the body diode is very large, 400ns!
This explains why it takes a long time for the output to fall down in absence of a resistive load. Changing the P-MOS with a faster recovery diode should enhance the time further.
360 ohm is a fairly low value to give a transition time as high as 100ns

 

[kathmandu]

360 ohm is a fairly low value to give a transition time as high as 100ns

Well, if I do a standard measurement (10% to 90% of the falling edge slope) the resulting time is lower than that. The 100ns it's measured from the begining of the slope till it reaches 0V (GND) level.

As I did mention before, there are a lot of parasitic capacitances due to poor PCB design thus I must say I'm very happy with the results.

Changing the P-MOS with a faster recovery diode should enhance the time further.

Do you mean using an external anti-parallel diode (schottky at best) to overcome the lazy body diode? Being a resistive load, I don't think the body diode would ever conduct though.