Fast to slow clock synchronization help

[kpk]

Hi
I have a 100MHz clk and a 20 MHz clk. The second clk is derived from the first clock. I have a posedge synchronization(Toggle) with whcih I am not able to meet the timings. So I have to make the synchronization faster. Can I synchronize in negedge? How to do it? What precautions should I take?

 

[E-design]

Can you post some diagrams to show your problem?

 

[subramanyam]

Hii ,
I am also suffering from this type of asynchronous clock domains. Can you please help me by sending some material on it . How to get the second clock in ur case from the first clock ?? and if u find the answer for ur problem can u plz share it with me ?

Thank you.

 

[elec-eng]

ch16
RTL HARDWARE DESIGN
USING VHDL
Coding for Efficiency, Portability,
and Scalability
ByONG P. CHU

It describes how to ternsfer signals from fast to slow clock domains and vice versa

 

[rameshsuthapalli]

Hi,

you can use synchronization circut. Though it is synchronous designs.

thanks,
ramesh

 

[skyfaye]

Here's a real design code I used.

///////////////////////////////////////////////////////////////////////////////////////
// module to get pulse signal across from fast clock domain to slow clock domain
///////////////////////////////////////////////////////////////////////////////////////

module pulse_cross (
hi_clk,
hi_reset,
lo_clk,
lo_reset,

pulse_in,
pulse_out
);

///////////////////////////////////////////////////////////////////////
// I/O definitions
///////////////////////////////////////////////////////////////////////

input hi_clk; //I: 212.5MHz system clock
input hi_reset; //I: reset in hi_clk domain
input lo_clk; //I: 125MHz cpu slave clock
input lo_reset; //I: reset in lo_clk domain

input pulse_in; //I: input pulse
output pulse_out; //O: output pulse
reg pulse_out;


//
// stretcher
//
reg din_reg_0, din_reg_1, din_reg_2;
reg strch_pulse;
always @ (posedge hi_clk)
begin
if (hi_reset) begin
din_reg_0 <= #1 1'b0;
din_reg_1 <= #1 1'b0;
din_reg_2 <= #1 1'b0;
strch_pulse <= #1 1'b0;
end
else begin
din_reg_0 <= #1 pulse_in;
din_reg_1 <= #1 din_reg_0;
din_reg_2 <= #1 din_reg_1;
strch_pulse <= #1 din_reg_0 | din_reg_1 | din_reg_2;
end
end

//
// synchronizer -- not necessary if fast/slow clock is in the same time domain (i.e. fast is multiple of slow AND both are generated by the same clock generator.)
//
reg sync_ff_0, sync_ff_1;
always @ (posedge lo_clk)
begin
sync_ff_0 <= #1 strch_pulse;
sync_ff_1 <= #1 sync_ff_0;
end

//
// output
//
reg dout_reg_0;
always @ (posedge lo_clk)
begin
if (lo_reset) begin
dout_reg_0 <= #1 1'b0;
pulse_out <= #1 1'b0;
end
else begin
dout_reg_0 <= #1 sync_ff_1;
pulse_out <= #1 ~dout_reg_0 & sync_ff_1;
end
end

endmodule // pulse_cross

 

[gurucharapathy]

Hi kpk,
You must use some pulse stretching circuit on the faster clock domain so that you can see it in the slower clock domain. Since your slow clock is derived from faster clock, the clocks are synchronous and hence no metastability worries.