CataM
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The PMOS below has 190mΩ at 125ºC junction temperature.a RDS(on) < 1Ω at the operating voltages indicated
The PMOS below has 190mΩ at 125ºC junction temperature.
I went to 3 amps output current, more than your application needs. The thing is that the Schottky removes about 0.5 V from the already dropped voltage.
The PMOS below has 190mΩ at 125ºC junction temperature.
I went to 3 amps output current, more than your application needs. The thing is that the Schottky removes about 0.5 V from the already dropped voltage.
You are right.
I have also included the package inductances (typical values) and the stray inductance might be between complementary emitter follower and MOSFET's gate. Now that explains why I have selected 1 ohm for the gate resistance.
You said (I quote): "i need a MOSFET without the built-in flyback diode"1. What's the purpose of the Schottky? If you remove it, it also works fine.
Increasing IDS does not mean anything. The PMOS is controlled by its Vsg voltage and hence by the control circuitry. Increasing IDS causes more voltage drop on its Rds(on) resistance. Eventually when you have a lot of current, the Vsd will be higher than Vsg-Vth and hence entering into its saturation region which will cause a lot of power loss.2. I can't quite wrap my head around why it works, because increasing Ids through R3 causes Vds -> Vcc, why is that not causing M1 to shut off prematurely?
e-design showed a better proposal in post #24.It seems that the logic gate would have to sink a whopping 143mA, would that constitute a problem when I build it? And can that energy be recovered in the name of efficiency?
Increasing IDS does not mean anything. The PMOS is controlled by its Vsg voltage and hence by the control circuitry. Increasing IDS causes more voltage drop on its Rds(on) resistance. Eventually when you have a lot of current, the Vsd will be higher than Vsg-Vth and hence entering into its saturation region which will cause a lot of power loss.
e-design showed a better proposal in post #24.
-Using T5 to provide the 10.5 V faster in order to not wait for the storage time of T1 is a master trick, but I think there is shoot-through for a little amount of time from VS1 through T5 through T1 and ground, isn't it ?
Here is a design using more old-school parts and keeping the pulse width out, close to the 100 nS of the input pulse. Rise and fall times around 22 nS.
Here is a design using more old-school parts and keeping the pulse width out, close to the 100 nS of the input pulse. Rise and fall times around 22 nS.
Watch attachment.As part of my understanding, did I divide the sections all right?
Watch attachment.
Here is a design using more old-school parts and keeping the pulse width out, close to the 100 nS of the input pulse. Rise and fall times around 22 nS.
BLUE trace is the gate pulse and 500nS/div.
The input pulse or GATE of PMOS?.
For initial testing, I would remove the PMOS and temporarily connect a 2n2 capacitor between the gate connection and GND. This will allow you to tweak the circuit to ensure that you get a good-looking gate-drive signal.
Once this is achieved, then start testing with the actual PMOS.
Do you have proper decoupling ?
Do you have proper layout ?
Of course, this would be very important; I agree.
Perhaps you could show us the layout?
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