fast fourier transform butterfly architecture problem..........

[nehsr]

Hello,

So this is my code for the butterfly architecture of my program.......... when compiled it says : component(40): "add": expecting ';'

component(41): "sub": expecting ';' and it continues so on for all the other components..........

my code is as follows:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
library work;
use work.fft_pkg.all;

entity butterfly is
port(
s1,s2 : in comp_array; --inputs
w :in comp_array; -- phase factor
x1_out,x2_out ut comp_array -- outputs
);
end butterfly;

architecture Behavioral of butterfly is

signal xxx : integer := 0;

type comp_array is array (0 to 7) of complex;
type comp_array2 is array (0 to 3) of complex;

function add (x1,x2,x3 : comp_array) return comp_array;
function sub (x1,x2,x3 : comp_array) return comp_array;
function mult (x1,x2,x3 : comp_array) return comp_array;
begin

--butterfly equations.
process

function add (x1,x2,x3 : comp_array) return comp_array is

function sub (x1,x2,x3 : comp_array) return comp_array is

function mult (x1,x2,x3 : comp_array) return comp_array is



begin
--1st stage equations:
x1(0) := s(0) add (s(4) mult w);
x1(1) := s(0) sub (s(4) mult w);
x1(2) := s(2) add (s(6) mult w);
x1(3) := s(2) sub (s(6) mult w);
x1(4) := s(1) add (s(5) mult w);
x1(5) := s(1) sub (s(5) mult w);
x1(6) := s(3) add (s(7) mult w);

--2nd stage equations:
x2(0) := x1(0) add (x1(2) mult w(0));
x2(2) := x1(0) sub (x1(2) mult w(0));
x2(3) := x1(1) add (x1(3) mult w(2));
x2(1) := x1(1) sub (x1(3) mult w(2));
x2(6) := x1(4) add (x1(6) mult w(0));
x2(4) := x1(4) sub (x1(6) mult w(0));
x2(7) := x1(5) add (x1(7) mult w(2));
x2(5) := x1(5) sub (x1(7) mult w(2));

--3rd stage equations:

x3(0) := x2(0) add (x2(4) mult w(0));
x3(4) := x2(0) sub (x2(4) mult w(0));
x3(1) := x2(1) add (x2(5) mult w(1));
X3(5) := x2(1) sub (x2(5) mult w(1));
x3(2) := x2(2) add (x2(6) mult w(2));
x3(6) := x2(2) sub (x2(6) mult w(2));
x3(3) := x2(3) add (x2(7) mult w(3));
x3(7) := x2(3) sub (x2(7) mult w(3));



end process;


end Behavioral;


Much appreciated if you could me please anyone..........

 

[TrickyDicky]

several problems.
1. The way you have written the code makes it look like the sub function is declared inside the add function, and the mult function is declared inside the sub function. Function are structured like this:

---

Code VHDL - [expand]
1
2
3
function my_function return something is
begin
end my_function;

---

From your code, you have not finished the functions off properly.

2. You have not called the functions properly. You need to call a function like this:

result := my_function(ip1, ip2, ip3);

3. Why have you declared you own add, sub and mult functions? these functions will probably already exist with +, - and *.

 

[nehsr]

thanks trickydicky............ i'll give it a go now.......... many thanks again mate............. btw, i forgot to mention its a vhdl code and am using modelsim for it........ d'y u reckon it should solve it?.

 

[TrickyDicky]

you can only solve it by writing the code corectly in the first place./