eliben
Newbie level 5
Hello,
In our application we have to receive and merge several proprietary serial channels (200 MHz) over fibers, and send all the data over Gigabit Ethernet. The bandwidth is ~60 MByte/s, sustained.
While generally sending this amount of data is possible over Gbit Ethernet, doing so in an embedded system isn't easy. That's because we need to send it by UDP or TCP, for which a TCP/UDP/IP stack is required (software).
Since the translation of the proprietary format is certainly done in an FPGA, I tried to calculate how to implement the whole process in an FPGA. For example, I can take an Altera Stratix II GX (with a built in Gbit Ethernet PHY), add Altera's MAC and use a TCP/IP stack running on the Nios II soft-core processor. Unfortunately, as Altera's appnote 440 shows, the maximal bandwidth attainable this way is only 15-17 MByte/s. For the sake of comparison, benchmarks of Gbit Ethernet adapters on PCs show a maximal bandwidth of 80-90 MByte/s.
However, I wouldn't like to build in a Pentium into the embedded system. Any suggestions / recommendations on how to solve the problem ?
Thanks in advance
In our application we have to receive and merge several proprietary serial channels (200 MHz) over fibers, and send all the data over Gigabit Ethernet. The bandwidth is ~60 MByte/s, sustained.
While generally sending this amount of data is possible over Gbit Ethernet, doing so in an embedded system isn't easy. That's because we need to send it by UDP or TCP, for which a TCP/UDP/IP stack is required (software).
Since the translation of the proprietary format is certainly done in an FPGA, I tried to calculate how to implement the whole process in an FPGA. For example, I can take an Altera Stratix II GX (with a built in Gbit Ethernet PHY), add Altera's MAC and use a TCP/IP stack running on the Nios II soft-core processor. Unfortunately, as Altera's appnote 440 shows, the maximal bandwidth attainable this way is only 15-17 MByte/s. For the sake of comparison, benchmarks of Gbit Ethernet adapters on PCs show a maximal bandwidth of 80-90 MByte/s.
However, I wouldn't like to build in a Pentium into the embedded system. Any suggestions / recommendations on how to solve the problem ?
Thanks in advance