Fast Big Memory- Camera - Help Needed For Design

[Sobakava]

I've to store 2.6MByte data (1.3M x 16bits) comes from a
parallel bus at 27MHz maximum data rate.

After I fill the RAM, I need to read it for transferring.

Reading from RAM will be asynchronous because I send data
over USB2.0 in 512byte packets. My USB controller will read
512bytes from RAM to it's FIFO and transfer it. And skips to
next 512bytes...

Data comes from an CMOS image sensor and I can not stop
it while I transfer the data. I can not stop sensor clock while
transferring pixel data. So, I need a memory buffer. This
can be a FIFO but I don't know how big FIFO is required.
My USB 2.0 controller has 512byte FIFO.

Direct connection of CMOS sensor and USB2.0 controller did not
work. I don't miss pixels in general but there are discontinuties in
data. (I can see some jumpings etc when I draw transferred pixel
data profiles to a chart at PC) I think USB controller misses
pixels while transferring previous 512bytes


I suppose, I can use asynchronous SRAM for storing data. Full
frame data takes 1.3M x 10bits and I need 1.3M x 16bits memory
can run at 27MHz. There are such chips but I don't know prices yet.
I plan to use two RAM blocks for double buffering. One is for storing
current frame, second is transferring to PC. After one frame is
filled with pixel data, it will start transfer it and start fill the other then
swap active RAMs again again...

What do you think? Probably using a SDRAM could be cheaper but
it is not so clear for me because I did not work with SDRAMs yet,
I suppose I need a SDRAM controller IC or I've to implement it in a
CPLD/FPGA. I is hard to implement a SDRAM controlller for using
a SDRAM like async-SRAM or like a very big FIFO?

I need advises from camera designers and digital designers and
here is the only place to find answers!!!

Regards

 

[robotman]

I have been working on something similar. I want to get to the data too, but I have the intention of multiplexing multiple image sensors over one link.

What I would do is to develop a SDRAM (DDR preferably) controller using a small FPGA. To help increase then bandwidth to the SDRAM, use burst mode or do some careful planning on how many read/writes can be done between refreshes (which you probably don't need because of all the accesses). By using this technique, you can keep banks open and even interleave between page swaps.

PM me if you want any additional info.

Just curious, what controller are you using for the host interface?

robotman

 

[Sobakava]

-Asynchronous SRAMs with 30-35ns access times-NEC and Toshiba has such SRAMS. If I could find a way to use SDRAM easily, it would be very nice for me...

I found some free SDRAM controller IPs on the net but I am not so experienced on FPGAs yet.

I need a module like this for SDRAM:
WriteCLK
ReadCLK
Data[0..15]
Address[0..x] (or and internal Address bus because my reading
and writings will be sequentally and I prefer memory address
increases in FPGA... For this, I need internal address pointer...
And there must be an address pointer reset input)

This would make my life easy. Anyway, may be later.


Could you tell me more a about Burst Mode of SDRAMs? Does it
mean writing data continuously without refreshing?

 

[Sobakava]

I found some documents on this...

https://www.xess.com/projects/Digital_Camera.pdf
"Xess has provided an SDRAM controller that makes the external 16Mx16 SDRAM look like simple SRAM. It handles refresh and bank interleaving and was available in a VHDL version. In its current state, the SDRAM controller does not support burst mode"


here is the datasheet.
**broken link removed**

Anyone has used it before? Can I implement
it on X|L|nX C00lRunner or Sp@rtan?