Faraday analog I/O pad: how to connect

[DoYouLinux]

Hi all,

Has anyone tried using Analog I/O pads from Faraday technology for 0.18-um UMC before ? I am starting to use it and I found something which is not clear to me.

First, it is indicated in the document that the connection from the "bonding pad" to the "core" of the circuit is linked directly by Metal 1 and Metal 2. I am wondering that, to connect them to the bonding pad and to my circuit, I need to use only Metal 1 or Metal 2. So, if I need to connect them with M6, for example, I need to create my own via starting from Metal 1 (or Metal 2) up to Metal 6 ?

Second, it seems to me that the "ground" pad is quite narrow (even with the cell for "core-limited design"). So, to support larger currents, can I just connect two or three ground pads side by side to each other ?

Thank you in advance all

DYLinux

 

[leo_o2]

Yes, you need to place more ground PADs for bigger current. I didn't check this process. But usually it is OK to use M6 for PAD connection.

 

[DoYouLinux]

Thanks for the information, Leo_o2

 

[zopeon]

Hi,
We are using Faraday 180nm analog I/O cells. We have AnalogESD 3.3V I/O only, that we have to connect to 1.8V analog core. I have two doubts
1. Will ESD be a problem becoz of the 3.3V ESD I/O and 1.8V core cells.
2. If I have my output common mode dc voltage at Vdd/2 i.e 0.9V( single ended supply) for core then how should I connect it to the 3.3V output pad? Do I need to convert my output to 3.3V power?

We had got the libraries through imec under europractice.
So if I have to ask faraday about it at which mailid should I send the mail as see onlu sales n hr mail ids?
thanks

 

[erikl]

...
2. If I have my output common mode dc voltage at Vdd/2 i.e 0.9V( single ended supply) for core then how should I connect it to the 3.3V output pad? Do I need to convert my output to 3.3V power?

No. Connect directly!

 

[zopeon]

@ erikl

Thank you very much. That makes life much easier!

 

[ESDSolutions]

Dear Zopeon

I do not know the details about the 3.3V analog ESD cells from Faraday but to me it seems dangerous to use the same cells for protection of the 1.8V core devices that are far more sensitive than the 3.3V devices.

You'd better ask for 1.8V specific ESD solutions in the specific technology node.
Let me know if they are not available from your library provider as at Sofics we specialize in providing ESD clamps that are not available from the libraries/foundries. We have fully characterized ESD cells available for TSMC & UMC 180nm.

Regards

EsdSolutions

 

[mikersia]

Using 3.3V ESD I/O for 1.8V core will create a problem,- ESD level will be low, because 1.8V MOSFEET oxide break down voltage (5...7V) is much lower, than 3.3V ESD protection target level (6...9V). How much,- depends from ESD structure, but below 1KV in any case. You can try to modify post I/O input chains to increase ESD protection level,- e.g. by adding a secondary (third?) ESD protection stage, say to add grounded NMOS (w=50...100um), followed by 100...500 Ohm NDIF resistor. But better to use proper I/O to guarantee satisfactory protection level.