False paths / Critical paths

[dBUGGER]

Hi all,
When designing with FPGA's how to assign some paths as false paths or multi cycle paths or critical paths etc? Where do we specify this information and how.
Thank you

Best Regards,

 

[tut]

All these constraints can be added in a Constraints file.
In case of Xilinx, these can be added in UCF (User constraint file).
Following links can help:
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If u r using ALTERA/Others, consult the user guide for entering constraints..

Hope it helps..

tut..

 

[Johnson]

dBUGGER:
Before P&R you need to do them in your synthesis software. What synthesise software do you are using?