speedman
Newbie level 6
false path on FIFO!
Hi all,
I have a dubt on FIFO synthesis.
If I generate by IP core gen in ISE, but in general if I build the fifo around a dp ram, may I declare a false path between the two clock internal ?
I don't know it.
Hi all,
I have a dubt on FIFO synthesis.
If I generate by IP core gen in ISE, but in general if I build the fifo around a dp ram, may I declare a false path between the two clock internal ?
I don't know it.