Failure of register generation after DC synthesis

[they]

Hi,
I coded some registers in my RTL. But after I synthesized it with DC, I can't find one of the registers in the gate level netlist generated.
May I know the possible reason this kind of problem happen?

 

[diablo1222]

Would you post your rtl code?

 

[they]

Would you post your rtl code?

Hi,
I am sorry, the entire RTL is too big and I think it is not very convenient for me to post it. Anyway, thanks for your concern.

 

[sr66]

If your registers are some how directly (or indirectly) not connected to any output ports , DC will remove them.

 

[diablo1222]

The reason maybe as below:
1) The input of register is float
2) The output of register isn't connected to output( directly or indirectly)
You can check the log file of synthesis to find the information about this issue.

 

[they]

Hi guys,
thank you very much!!!

 

[haosg]

right, maybe the register is not used, or they are constant value.
so don't warry, you can run formal check to see if the functional is wrong

 

[they]

Another question:
I run a synthesis with 2 compile.
The first compile is run withou any option, and the "check_design" command reports some warnings.
After that, the compiled design is "ungroup -flatten -all" and then compile again with options "-incremental_mapping -map_effort high". The second compile is then follow by a "check_design". There is no any warnings found in the second "check_design" report. So is that means the second compile has fix the problems (warnings) in found in the first compile?

 

[funzero]

may be your coding error