failure in clock domains (Xilinx)

[spman]

Hi friends,
What is problem in this design? The Clk net isn't detected in clock domains (constraint).

module top(InputClk, OutputClk, ...);
	input	InputClk;
	output	OutputClk;
	
	wire ClkToDCM;
	wire ClkToBUFG;
	wire Clk;
	
	IBUFG IBUFG_Ins(.I(InputClk), .O(ClkToDCM));
	DCM	DCM_Ins(.CLKIN(ClkToDCM), .CLKFX(ClkToBUFG));
	BUFG	BUFG_Ins(.I(ClkToBUFG), .O(Clk));
	assign	OutputClk = Clk;
	
	always @(posedge Clk) begin
		//state machine ...
	end

UCF :

INST DCM_Ins CLKFX_MULTIPLY = 3;
INST DCM_Ins CLKFX_DIVIDE = 1;
INST DCM_Ins CLK_FEEDBACK = NONE;

I checked the design in FPGA Editor. The Clk isn't trimmed. It is routed to all CLBs. My FPGA is Spartan3.

 

[gongdori]

Is the feedback port in DCM connected?
Also, DCM has reset requirement, I think...

 

[spman]

Is the feedback port in DCM connected?

No! according to XAPP462 "The feedback input is required unless the Digital Frequency Synthesis outputs, CLKFX or CLKFX180, are used stand-alone."

 

[gongdori]

Oh, I see. I didn't know that CLKFB is not needed when only CLKFX or CLKFX180 are used.

Is it the issue with real hardware or simulation?
If hardware, do you reset DCM after the input clock gets stabilized?

 

[spman]

This problelem appears when i use DCM.
Even in this simple design :

module counter(InputClk, ResetL, Dir, Out);
	input	InputClk, ResetL, Dir;
	output	[3:0] Out;
	reg		[3:0] Out;
	
	wire ClkToDCM, ClkToBUFG, Clk;
	
	IBUFG IBUFG_Ins(.I(InputClk), .O(ClkToDCM));
	DCM	DCM_Ins(.CLKIN(ClkToDCM), .CLK0(ClkToBUFG), .CLKFB(Clk));
	BUFG	BUFG_Ins(.I(ClkToBUFG), .O(Clk));
	
	always	@(posedge Clk or negedge ResetL)
		if (!ResetL)
			Out <= 0;
		else if (Dir)
			Out <= Out + 1;
		else
			Out <= Out - 1;
endmodule

 

[gongdori]

So, it is an actual problem with the hardware, right?
Do you reset the DCM?

 

[spman]

So, it is an actual problem with the hardware, right?

No. The design works correctly after implementation.

Do you reset the DCM?

No, i don't