facing problems in synthesis

[Partha Mukherjee]

while synthesizing the register file unit for ADSP 21020 I found that synthesis takes exponential amount of time... I try to found in which part this mess occurs and find that while taking the REGISTER WRITE part along with REGISTER READ and TRI STATE BUFFER etc for synthesis. The Verilog code of write part is as follows :

always @(posedge clk)
      begin
	 if(wr1)
	   begin
		if(addr1_w < 8)
		  begin
		   if(srrfl)
		      alternate_regfile[addr1_w] <= data_in1;
		   else
		      primary_regfile[addr1_w] <= data_in1;    
		  end
		else if(addr1_w < 16 && addr1_w >= 8)
		  begin
		   if(srrfh)
		      alternate_regfile[addr1_w] <= data_in1;
		   else
		      primary_regfile[addr1_w] <= data_in1;
	        end
		   else
		    $display("Invalid Register Number"); 
	  end

. ...............


Here alternate_regfile and primary_regfile are two 'reg' variables (each indicates 16 registers of 40 bit each) declared as

reg [39:0] primary_regfile [3:0]; // primary register file
reg [39:0] alternate_regfile [3:0]; //secondary register file
input [39: 0] data_in1,
input [3:0] addr1_w // 4 bit address selection input to select register number
// from 0 to 15 for writing.

input srrfl and srrfh are two input flags to select frist half (0 to 7) or second half
(8 to 15) of primary/ secondary register file.

input wr1 //input signal to enable write in primary_regfile[addr1_w] or
alternate_regfile[addr1_w] . (register from 0 to 15)

There are five such blocks (as register file unit interacts with data and program memory buses and other computational unit such as ALU/shifter etc..)..

after implementing the first block I come to the following problems:

1. Found area constraint ratio of 100 (+ 5) on block register_file, actual ratio is 15.

2. INFO:Xst:738 - HDL ADVISOR - 640 flip-flops were inferred for signal <alternate_regfile>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported.

INFO:Xst:738 - HDL ADVISOR - 640 flip-flops were inferred for signal <primary_regfile>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported.

3.Number of bonded IOBs: 411 out of 408 100% > 100% of resource.

While implementing the second such block (addr2 and addr2_w) synthesis takes exponential time..... please help how should I restructure the code.

I am working on XCV1000-6bg560.

 

[echo47]

Please post a complete module that can be compiled and synthesized.

You posted two similar messages, perhaps by mistake. You can delete the other one.

 

[nand_gates]

There is discrepancy between the code you have posted and the discription
you have given!

Accoding to ur discription

reg [39:0] primary_regfile [3:0]; // primary register file
reg [39:0] alternate_regfile [3:0]; //secondary register file
input [39: 0] data_in1,
input [3:0] addr1_w // 4 bit address selection input to select register number
// from 0 to 15 for writing.

shuld be ....
reg [39:0] primary_regfile [7:0]; // primary register file 8 locations
reg [39:0] alternate_regfile [7:0]; //secondary register file 8 locations
input [39: 0] data_in1,
input [3:0] addr1_w // 4 bit address selection input to select register number
// from 0 to 15 for writing.

I dont think that you need srrfh and srrfl flags....

Here is the corrected code...

always @(posedge clk) begin
   if (wr1) begin
      if (addr1_w[3]) // addr1_w = 8 to 15
         alternate_regfile[addr1_w[2:0]] <= data_in1;
      else // addr1_w = 0 to 7
        primary_regfile[addr1_w[2:0]] <= data_in1;
   end
end // always @ (posedge clk)

Hope this helps

 

[AH Ling]

always @(posedge clk) begin
if (wr1) begin
if (addr1_w[3]) // addr1_w = 8 to 15
alternate_regfile[addr1_w[2:0]] <= data_in1;
else // addr1_w = 0 to 7
primary_regfile[addr1_w[2:0]] <= data_in1;
end **
end // always @ (posedge clk)

with reference to your coding as above, your coding will synthesize hardware that posses hazard to unknown condition.... the hardware will only consider about wr1 at logic high. it is better if you set the address registers as no change if wr1 is logic 0....at functional level, there may not be error, but at real hardware, it may cause metastable state....suggest u add this few lines after **
*********************************
else begin

alternate_regfile <= alternate_regfile;
primary_regfile <= primary_regfile ;

end
**********************************

 

[ManojG]

Adding a code like this will create a feedback path in real hardware. Does this feedback path will create any problems?

else begin

alternate_regfile <= alternate_regfile;
primary_regfile <= primary_regfile ;

end

 

[Partha Mukherjee]

How should I add the code as attachment because when I want to attach it
a message comes

"The Extension v is not allowed". I have tried to attach it wrining the code on a wordpad as .rtf file but the same message comes as

"The Extension rtf is not allowed".

Please post a complete module that can be compiled and synthesized.

You posted two similar messages, perhaps by mistake. You can delete the other one.