f u use stacked vias,the parasitic capacitance will reduce?

[dazzling_deepika]

stacked structures?

is it true that if u use stacked vias,the overall parasitic capacitance will reduce?

and why are many small contacts preferred over one big contact?

 

[faizalism]

Re: stacked structures?

Do you mean, via1 connect with via2 connect with via3.....via6? So, the via connected each other.

The contact size is fixed by the foundry. You need to put many contacts for the yields purposed and also it can reduce the resistance. It also based on the current capacity.

 

[diemilio]

Re: stacked structures?

Yes, it's true.

Stacked vias minimize the parasitic capacitance in between two different metal layers because when you put them one on top of each other, the effective area between those layers is almost zero, so there's no room for the caps to form.


See attached pic.

Hope this helps,

diemilio

 

[sat]

stacked structures?

Note that - this is about Parasitic-Self-Cap.
It is not talking about parasitic cap between two different nets.

 

[Colbhaidh]

Re: stacked structures?

Multiple small sized contacts are generally required as the fabrication process for ICs cannot use large contacts. This is due to two effects.
1. The contact/via process uses a tungsten plug - this is where the contact hole is filled with tungsten all opver the Si wafer. The tungsten is then polished off using CMP to leave just the tunsten plug inside the contact. It the contact is huge, this process will not work properly and could leave residual polishing slurry inside the top of the contact giving reliability concerns. A second effect of this is that for a large contact where the tungsten was polished off, the plug will be recessesed below the top of the isolation. Around the edge just inside the top will be a sliver of tungsten that can become detached and cause shorts elsewhere on the Si wafer.

2. The contact etch process is tuned to remove the oxide where the contact is to be formed, which will be a small deep hole. Because the exposed area to be etched is relatively small with respect to the entire wafer, the selectivity of this process to the material to which the base of the contact will touch (Poly silicide or active silicide) has to be such that the time taken to ensure all oxide is removed completely from all contacts everywhere on the wafer does not destroy the underlying material where the first contact to be cleared is. For example the centre of the wafer may etch faster than the edge, so centre contacts are cleared first and thus the material at the bottom of the contact is exposed to the plasma longer than for edge contacts.
If you use a very large contact, chances are this will clear long before the smaller ones and so its underlying material may be destroyed.