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F.E.C. , parity generator.

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Titormos

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Hello,
I am currently working on a 10 Gbps optic fiber connection that is going to have a FEC circuit.
I am done with many parts of the circuit but I am stuck at the parity generator.

this is how it is described.
it actually has an example with the input and output of this mathematical expression and obviously you don't get a correct parity when you interpret each symbol as a mathematical one.
x^32 is a sift left as it says
and the problem is the modulo operator. I've tried many ways of calculating that but nothing was right.
one of them is the creation of a 2112 bit wide(that the input to the parity generator) shift register that "xors" the bits specified by the g(x) polynomial, which results in a false result after 2112 shifts (also at 2112-32 shifts)

any help is appreciated.
thanks in advance.

P.S. I am not sure if this is on the right section of the forum.

edit: I wanted to explain that p(x) is the parity and that is the thing I want to calculate. I don't know what the modulo operation means.
 
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