Extract spice netlist from Prime Time

[TXY-007]

Dear all,

I extracted an inverter's HSPICE netlist with the write_spice_deck instruction from PT, and then used HSPICE and PT to perform delay analysis on the inverter. But for the propagation delay of the inverter, the result obtained by PT is much larger than that of HSPICE. I would like to know how to solve this issue.
This is the tcl script I execute in PT. The transistor models and subcircuits I used are all from Nangate 45nm open source library.

set library_name NangateOpenCellLibrary
set link_library [list * ./Nangate_synthetic_lib.db]

read_verilog  INV_bench.v
current_design "INV_bench"

link_design

set_max_area 0.53
set CLK_PERIOD 5
set CLK "A"
create_clock -period $CLK_PERIOD [get_ports $CLK]
set_clock_transition -rise 0.003 [get_clocks $CLK]
set_clock_transition -fall 0.003 [get_clocks $CLK]

set_max_delay 0.1 -from A -to ZN

write_spice_deck -output my_output.sp -header model.sp -logic_one_name VDD -logic_one_voltage 1.1 -logic_zero_name VSS -logic_zero_voltage 0 -sub_circuit_file inverter.sp [get_timing_paths -from A -to ZN]

report_timing
quit

Thanks a alot.
Best,
XY

 

[oratie]

Does the subcircuits spice netlist contains RC parasitics? Or they just lvs netlist (only transistors)?

 

[TXY-007]

Does the subcircuits spice netlist contains RC parasitics? Or they just lvs netlist (only transistors)?

Dear Oratio，

Yes, the subcircuit netlist contains only RC parasitics, and the header file only contains the transistor model. Here are the details about my subcircuit. Could you please tell me is there anything else I need to add？

.SUBCKT INV_X1 VDD VSS A ZN
*.PININFO VDD:P VSS:G A:I ZN:O
*.EQN ZN=!A
M_M1 N_ZN_M0_d N_A_M0_g N_VDD_M0_s VDD PMOS_VTL W=0.630000U L=0.050000U
M_M0 N_ZN_M1_d N_A_M1_g N_VSS_M1_s VSS NMOS_VTL W=0.415000U L=0.050000U
C_x_PM_INV_X1%VDD_c0 x_PM_INV_X1%VDD_31 VSS 4.13109e-17
C_x_PM_INV_X1%VDD_c1 x_PM_INV_X1%VDD_19 VSS 2.61599e-16
C_x_PM_INV_X1%VDD_c2 x_PM_INV_X1%VDD_18 VSS 1.89932e-17
C_x_PM_INV_X1%VDD_c3 N_VDD_M0_s VSS 3.88255e-17
C_x_PM_INV_X1%VDD_c4 x_PM_INV_X1%VDD_12 VSS 1.92462e-17
C_x_PM_INV_X1%VDD_c5 x_PM_INV_X1%VDD_11 VSS 2.334e-16
C_x_PM_INV_X1%VDD_c6 x_PM_INV_X1%VDD_8 VSS 5.52247e-16
R_x_PM_INV_X1%VDD_r7 VDD x_PM_INV_X1%VDD_31 0.13879
R_x_PM_INV_X1%VDD_r8 VDD x_PM_INV_X1%VDD_28 0.392137
R_x_PM_INV_X1%VDD_r9 VDD x_PM_INV_X1%VDD_19 0.13879
R_x_PM_INV_X1%VDD_r10 x_PM_INV_X1%VDD_19 VDD 3.84471
R_x_PM_INV_X1%VDD_r11 x_PM_INV_X1%VDD_18 x_PM_INV_X1%VDD_28 0.0752999
R_x_PM_INV_X1%VDD_r12 x_PM_INV_X1%VDD_31 x_PM_INV_X1%VDD_18 0.704118
R_x_PM_INV_X1%VDD_r13 x_PM_INV_X1%VDD_28 N_VDD_M0_s 0.719286
R_x_PM_INV_X1%VDD_r14 x_PM_INV_X1%VDD_12 VDD 0.140282
R_x_PM_INV_X1%VDD_r15 x_PM_INV_X1%VDD_11 VDD 0.143516
R_x_PM_INV_X1%VDD_r16 x_PM_INV_X1%VDD_11 x_PM_INV_X1%VDD_12 7.68941
R_x_PM_INV_X1%VDD_r17 x_PM_INV_X1%VDD_8 VDD 8.51647
C_x_PM_INV_X1%VSS_c0 VSS VSS 2.61599e-16
C_x_PM_INV_X1%VSS_c1 x_PM_INV_X1%VSS_18 VSS 1.89932e-17
C_x_PM_INV_X1%VSS_c2 x_PM_INV_X1%VSS_17 VSS 4.14709e-17
C_x_PM_INV_X1%VSS_c3 N_VSS_M1_s VSS 4.35792e-17
C_x_PM_INV_X1%VSS_c4 x_PM_INV_X1%VSS_10 VSS 5.52247e-16
C_x_PM_INV_X1%VSS_c5 x_PM_INV_X1%VSS_9 VSS 1.92462e-17
C_x_PM_INV_X1%VSS_c6 x_PM_INV_X1%VSS_8 VSS 2.334e-16
R_x_PM_INV_X1%VSS_r7 VSS x_PM_INV_X1%VSS_29 0.392137
R_x_PM_INV_X1%VSS_r8 x_PM_INV_X1%VSS_18 x_PM_INV_X1%VSS_29 0.0752999
R_x_PM_INV_X1%VSS_r9 x_PM_INV_X1%VSS_18 VSS 0.178824
R_x_PM_INV_X1%VSS_r10 VSS x_PM_INV_X1%VSS_17 0.13879
R_x_PM_INV_X1%VSS_r11 x_PM_INV_X1%VSS_17 VSS 0.525294
R_x_PM_INV_X1%VSS_r12 x_PM_INV_X1%VSS_29 N_VSS_M1_s 1.47929
R_x_PM_INV_X1%VSS_r13 x_PM_INV_X1%VSS_10 VSS 8.51647
R_x_PM_INV_X1%VSS_r14 x_PM_INV_X1%VSS_9 VSS 0.140282
R_x_PM_INV_X1%VSS_r15 x_PM_INV_X1%VSS_8 VSS 0.143516
R_x_PM_INV_X1%VSS_r16 x_PM_INV_X1%VSS_8 x_PM_INV_X1%VSS_9 7.68941
C_x_PM_INV_X1%A_c0 x_PM_INV_X1%A_18 VSS 1.01215e-17
C_x_PM_INV_X1%A_c1 x_PM_INV_X1%A_9 VSS 4.4957e-17
C_x_PM_INV_X1%A_c2 N_A_M0_g VSS 8.65621e-17
C_x_PM_INV_X1%A_c3 N_A_M1_g VSS 6.49671e-17
R_x_PM_INV_X1%A_r4 x_PM_INV_X1%A_11 x_PM_INV_X1%A_18 3.9
R_x_PM_INV_X1%A_r5 x_PM_INV_X1%A_9 x_PM_INV_X1%A_11 25.0012
R_x_PM_INV_X1%A_r6 x_PM_INV_X1%A_9 A 0.135714
R_x_PM_INV_X1%A_r7 x_PM_INV_X1%A_5 x_PM_INV_X1%A_18 1.95
R_x_PM_INV_X1%A_r8 x_PM_INV_X1%A_5 N_A_M0_g 56.94
R_x_PM_INV_X1%A_r9 x_PM_INV_X1%A_1 x_PM_INV_X1%A_18 1.95
R_x_PM_INV_X1%A_r10 x_PM_INV_X1%A_1 N_A_M1_g 40.17
C_x_PM_INV_X1%ZN_c0 N_ZN_M1_d VSS 1.95828e-16
R_x_PM_INV_X1%ZN_r1 ZN N_ZN_M0_d 2.21
R_x_PM_INV_X1%ZN_r2 N_ZN_M1_d ZN 1.09
.ENDS

 

[ThisIsNotSam]

I suspect your 3ps transition time has something to do with it. PT probably has difficulty modelling it.

 

[TXY-007]

I suspect your 3ps transition time has something to do with it. PT probably has difficulty modelling it.

Thanks for your reply.
I changed the transition time to 0.1ns, but the results are still different.

 

[ThisIsNotSam]

Thanks for your reply.
I changed the transition time to 0.1ns, but the results are still different.

how different? by how much? some discrepancy is expected, afterall SPICE simulation is much more accurate

 

[TXY-007]

how different? by how much? some discrepancy is expected, afterall SPICE simulation is much more accurate

Simulations show that the results of PT are several times larger than HSPICE.
I've tried a few ways to solve it, but I found something very strange.

If I apply a clock to the input of the inverter in this way

set CLK_PERIOD 5
set CLK "A"
create_clock -period $CLK_PERIOD [get_ports $CLK]
set_clock_transition -rise 0.1 [get_clocks $CLK]
set_clock_transition -fall 0.1 [get_clocks $CLK]

The transition time of the power supply of A in the spice netlist I extracted is fixed at 0ns, no matter how I change the clock transition time in the tcl script.

If I change set_clock_transition to set_input_transition

set PERIOD 5
create_clock -period $PERIOD [get_ports A]
set_input_transition -rise 0.1 [get_ports A]
set_input_transition -fall 0.1 [get_ports A]

The transition time of the power supply of A in the spice netlist I extracted is the same as PT, but in this way, I still get the result that the delay obtained by PT simulation is still several times larger than the delay of HSPICE.

If you have any other suggestions, please let me know. Thank you so much.

 

[ThisIsNotSam]

show us the entire spice file you are using for HSPICE simulation

 

[TXY-007]

Here is the spice netlist I extracted from PT. It includes the main circuit and transistor models. I omitted a lot of unnecessary information, such as comments.

.model  NMOS_VTL  nmos  (level = 54
+tnom = 27         epsrox = 3.9
+eta0 = 0.006     nfactor = 2.1    wint = 5e-09
+cgso = 1.1e-10    cgdo = 1.1e-10    xl = -2e-08
+toxe = 1.14e-09    toxp = 1e-09    toxm = 1.14e-09    toxref = 1.14e-09
+dtox = 0.14e-09    lint = 3.75e-09
+vth0 = 0.322       k1 = 0.4   u0 = 0.045   vsat = 148000
+rdsw = 155        ndep = 3.4e+18    xj = 1.98e-08
+version = 4.0             binunit = 1               paramchk= 1               mobmod  = 0             
+capmod  = 2               igcmod  = 1               igbmod  = 1               geomod  = 1             
+diomod  = 1               rdsmod  = 0               rbodymod= 1               rgatemod= 1             
+permod  = 1               acnqsmod= 0               trnqsmod= 0                 
+ll      = 0               wl      = 0               lln     = 1               wln     = 1             
+lw      = 0               ww      = 0               lwn     = 1               wwn     = 1             
+lwl     = 0               wwl     = 0               xpart   = 0                   
+k2      = 0               k3      = 0             
+k3b     = 0               w0      = 2.5e-006        dvt0    = 1               dvt1    = 2             
+dvt2    = 0               dvt0w   = 0               dvt1w   = 0               dvt2w   = 0             
+dsub    = 0.1             minv    = 0.05            voffl   = 0               dvtp0   = 1e-010       
+dvtp1   = 0.1             lpe0    = 0               lpeb    = 0                   
+ngate   = 3e+20           nsd     = 2e+020          phin    = 0             
+cdsc    = 0               cdscb   = 0               cdscd   = 0               cit     = 0             
+voff    = -0.13           etab    = 0             
+vfb     = -0.55           ua      = 6e-010          ub      = 1.2e-018     
+uc      = 0               a0      = 1               ags     = 0             
+a1      = 0               a2      = 1               b0      = 0               b1      = 0             
+keta    = 0.04            dwg     = 0               dwb     = 0               pclm    = 0.02         
+pdiblc1 = 0.001           pdiblc2 = 0.001           pdiblcb = -0.005          drout   = 0.5           
+pvag    = 1e-020          delta   = 0.01            pscbe1  = 8.14e+008       pscbe2  = 1e-007       
+fprout  = 0.2             pdits   = 0.08            pditsd  = 0.23            pditsl  = 2300000       
+rsh     = 5               rsw     = 80              rdw     = 80           
+rdswmin = 0               rdwmin  = 0               rswmin  = 0               prwg    = 0             
+prwb    = 0               wr      = 1               alpha0  = 0.074           alpha1  = 0.005         
+beta0   = 30              agidl   = 0.0002          bgidl   = 2.1e+009        cgidl   = 0.0002       
+egidl   = 0.8             aigbacc = 0.012           bigbacc = 0.0028          cigbacc = 0.002         
+nigbacc = 1               aigbinv = 0.014           bigbinv = 0.004           cigbinv = 0.004         
+eigbinv = 1.1             nigbinv = 3               aigc    = 0.02            bigc    = 0.0027       
+cigc    = 0.002           aigsd   = 0.02            bigsd   = 0.0027          cigsd   = 0.002         
+nigc    = 1               poxedge = 1               pigcd   = 1               ntox    = 1             
+xrcrg1  = 12              xrcrg2  = 5             
+cgbo    = 2.56e-011       cgdl    = 2.653e-010   
+cgsl    = 2.653e-010      ckappas = 0.03            ckappad = 0.03            acde    = 1             
+moin    = 15              noff    = 0.9             voffcv  = 0.02         
+kt1     = -0.11           kt1l    = 0               kt2     = 0.022           ute     = -1.5         
+ua1     = 4.31e-009       ub1     = 7.61e-018       uc1     = -5.6e-011       prt     = 0             
+at      = 33000         
+fnoimod = 1               tnoimod = 0             
+jss     = 0.0001          jsws    = 1e-011          jswgs   = 1e-010          njs     = 1             
+ijthsfwd= 0.01            ijthsrev= 0.001           bvs     = 10              xjbvs   = 1             
+jsd     = 0.0001          jswd    = 1e-011          jswgd   = 1e-010          njd     = 1             
+ijthdfwd= 0.01            ijthdrev= 0.001           bvd     = 10              xjbvd   = 1             
+pbs     = 1               cjs     = 0.0005          mjs     = 0.5             pbsws   = 1             
+cjsws   = 5e-010          mjsws   = 0.33            pbswgs  = 1               cjswgs  = 3e-010       
+mjswgs  = 0.33            pbd     = 1               cjd     = 0.0005          mjd     = 0.5           
+pbswd   = 1               cjswd   = 5e-010          mjswd   = 0.33            pbswgd  = 1             
+cjswgd  = 5e-010          mjswgd  = 0.33            tpb     = 0.005           tcj     = 0.001         
+tpbsw   = 0.005           tcjsw   = 0.001           tpbswg  = 0.005           tcjswg  = 0.001         
+xtis    = 3               xtid    = 3             
+dmcg    = 0               dmci    = 0               dmdg    = 0               dmcgt   = 0             
+dwj     = 0               xgw     = 0               xgl     = 0             
+rshg    = 0.4             gbmin   = 1e-010          rbpb    = 5               rbpd    = 15           
+rbps    = 15              rbdb    = 15              rbsb    = 15              ngcon   = 1)
* Customized PTM 45 PMOS
.model  PMOS_VTL  pmos  (level = 54
+vth0    = -0.3021           toxref  = 1.26e-009      vsat    = 69000
+toxe    = 1.26e-009        toxp    = 1.0e-009          toxm    = 1.26e-009     
+dtox    = 2.6e-010          epsrox  = 3.9             wint    = 5e-009          lint    = 3.75e-009
+version = 4.0             binunit = 1               paramchk= 1               mobmod  = 0             
+capmod  = 2               igcmod  = 1               igbmod  = 1               geomod  = 1             
+diomod  = 1               rdsmod  = 0               rbodymod= 1               rgatemod= 1             
+permod  = 1               acnqsmod= 0               trnqsmod= 0             
+tnom    = 27               
+ll      = 0               wl      = 0               lln     = 1               wln     = 1             
+lw      = 0               ww      = 0               lwn     = 1               wwn     = 1             
+lwl     = 0               wwl     = 0               xpart   = 0               toxref  = 1.3e-009     
+xl       = -20e-9
+k1      = 0.4             k2      = -0.01           k3      = 0             
+k3b     = 0               w0      = 2.5e-006        dvt0    = 1               dvt1    = 2             
+dvt2    = -0.032          dvt0w   = 0               dvt1w   = 0               dvt2w   = 0             
+dsub    = 0.1             minv    = 0.05            voffl   = 0               dvtp0   = 1e-011       
+dvtp1   = 0.05            lpe0    = 0               lpeb    = 0               xj      = 1.98e-008     
+ngate   = 2e+020          ndep    = 2.44e+018        nsd     = 2e+020          phin    = 0             
+cdsc    = 0               cdscb   = 0               cdscd   = 0               cit     = 0             
+voff    = -0.126          nfactor = 2.22             eta0    = 0.0055          etab    = 0             
+vfb     = 0.55            u0      = 0.02            ua      = 2e-009          ub      = 5e-019       
+uc      = 0               a0      = 1               ags     = 1e-020       
+a1      = 0               a2      = 1               b0      = 0               b1      = 0             
+keta    = -0.047          dwg     = 0               dwb     = 0               pclm    = 0.12         
+pdiblc1 = 0.001           pdiblc2 = 0.001           pdiblcb = 3.4e-008        drout   = 0.56         
+pvag    = 1e-020          delta   = 0.01            pscbe1  = 8.14e+008       pscbe2  = 9.58e-007     
+fprout  = 0.2             pdits   = 0.08            pditsd  = 0.23            pditsl  = 2300000       
+rsh     = 5               rdsw    = 155             rsw     = 75              rdw     = 75           
+rdswmin = 0               rdwmin  = 0               rswmin  = 0               prwg    = 0             
+prwb    = 0               wr      = 1               alpha0  = 0.074           alpha1  = 0.005         
+beta0   = 30              agidl   = 0.0002          bgidl   = 2.1e+009        cgidl   = 0.0002       
+egidl   = 0.8             aigbacc = 0.012           bigbacc = 0.0028          cigbacc = 0.002         
+nigbacc = 1               aigbinv = 0.014           bigbinv = 0.004           cigbinv = 0.004         
+eigbinv = 1.1             nigbinv = 3               aigc    = 0.010687        bigc    = 0.0012607     
+cigc    = 0.0008          aigsd   = 0.010687        bigsd   = 0.0012607       cigsd   = 0.0008       
+nigc    = 1               poxedge = 1               pigcd   = 1               ntox    = 1             
+xrcrg1  = 12              xrcrg2  = 5             
+cgso    = 1.1e-010        cgdo    = 1.1e-010        cgbo    = 2.56e-011       cgdl    = 2.653e-010   
+cgsl    = 2.653e-010      ckappas = 0.03            ckappad = 0.03            acde    = 1             
+moin    = 15              noff    = 0.9             voffcv  = 0.02         
+kt1     = -0.11           kt1l    = 0               kt2     = 0.022           ute     = -1.5         
+ua1     = 4.31e-009       ub1     = 7.61e-018       uc1     = -5.6e-011       prt     = 0             
+at      = 33000         
+fnoimod = 1               tnoimod = 0             
+jss     = 0.0001          jsws    = 1e-011          jswgs   = 1e-010          njs     = 1             
+ijthsfwd= 0.01            ijthsrev= 0.001           bvs     = 10              xjbvs   = 1             
+jsd     = 0.0001          jswd    = 1e-011          jswgd   = 1e-010          njd     = 1             
+ijthdfwd= 0.01            ijthdrev= 0.001           bvd     = 10              xjbvd   = 1             
+pbs     = 1               cjs     = 0.0005          mjs     = 0.5             pbsws   = 1             
+cjsws   = 5e-010          mjsws   = 0.33            pbswgs  = 1               cjswgs  = 3e-010       
+mjswgs  = 0.33            pbd     = 1               cjd     = 0.0005          mjd     = 0.5           
+pbswd   = 1               cjswd   = 5e-010          mjswd   = 0.33            pbswgd  = 1             
+cjswgd  = 5e-010          mjswgd  = 0.33            tpb     = 0.005           tcj     = 0.001         
+tpbsw   = 0.005           tcjsw   = 0.001           tpbswg  = 0.005           tcjswg  = 0.001         
+xtis    = 3               xtid    = 3             
+dmcg    = 0               dmci    = 0               dmdg    = 0               dmcgt   = 0             
+dwj     = 0               xgw     = 0               xgl     = 0             
+rshg    = 0.4             gbmin   = 1e-010          rbpb    = 5               rbpd    = 15           
+rbps    = 15              rbdb    = 15              rbsb    = 15              ngcon   = 1   )         


.prot
.include "subcircuit_inverter.sp"
.unprot
.include "output_stim.sp"
vvdd vdd 0 1.1
.global vss
vvss vss 0 0
.temp 25

vA_INV1/A    A    INV1/A    0
c00000    A    0    3.1074e-16

vZN_INV1/ZN    ZN    INV1/ZN    0
c00001    INV1/ZN    0    3.1074e-16

xINV1 INV1_VDD VSS INV1/A INV1/ZN INV_X1
vINV1_VDD INV1_VDD 0 1.1

c00002    ZN    0    1e-18

.end

 

[TXY-007]

show us the entire spice file you are using for HSPICE simulation

This is subcircuit_inverter.sp I executed

.SUBCKT INV_X1 VDD VSS A ZN
*.PININFO VDD:P VSS:G A:I ZN:O
*.EQN ZN=!A
M_M1 N_ZN_M0_d N_A_M0_g N_VDD_M0_s VDD PMOS_VTL W=0.630000U L=0.050000U
M_M0 N_ZN_M1_d N_A_M1_g N_VSS_M1_s VSS NMOS_VTL W=0.415000U L=0.050000U
C_x_PM_INV_X1%VDD_c0 x_PM_INV_X1%VDD_31 VSS 4.13109e-17
C_x_PM_INV_X1%VDD_c1 x_PM_INV_X1%VDD_19 VSS 2.61599e-16
C_x_PM_INV_X1%VDD_c2 x_PM_INV_X1%VDD_18 VSS 1.89932e-17
C_x_PM_INV_X1%VDD_c3 N_VDD_M0_s VSS 3.88255e-17
C_x_PM_INV_X1%VDD_c4 x_PM_INV_X1%VDD_12 VSS 1.92462e-17
C_x_PM_INV_X1%VDD_c5 x_PM_INV_X1%VDD_11 VSS 2.334e-16
C_x_PM_INV_X1%VDD_c6 x_PM_INV_X1%VDD_8 VSS 5.52247e-16
R_x_PM_INV_X1%VDD_r7 VDD x_PM_INV_X1%VDD_31 0.13879
R_x_PM_INV_X1%VDD_r8 VDD x_PM_INV_X1%VDD_28 0.392137
R_x_PM_INV_X1%VDD_r9 VDD x_PM_INV_X1%VDD_19 0.13879
R_x_PM_INV_X1%VDD_r10 x_PM_INV_X1%VDD_19 VDD 3.84471
R_x_PM_INV_X1%VDD_r11 x_PM_INV_X1%VDD_18 x_PM_INV_X1%VDD_28 0.0752999
R_x_PM_INV_X1%VDD_r12 x_PM_INV_X1%VDD_31 x_PM_INV_X1%VDD_18 0.704118
R_x_PM_INV_X1%VDD_r13 x_PM_INV_X1%VDD_28 N_VDD_M0_s 0.719286
R_x_PM_INV_X1%VDD_r14 x_PM_INV_X1%VDD_12 VDD 0.140282
R_x_PM_INV_X1%VDD_r15 x_PM_INV_X1%VDD_11 VDD 0.143516
R_x_PM_INV_X1%VDD_r16 x_PM_INV_X1%VDD_11 x_PM_INV_X1%VDD_12 7.68941
R_x_PM_INV_X1%VDD_r17 x_PM_INV_X1%VDD_8 VDD 8.51647
C_x_PM_INV_X1%VSS_c0 VSS VSS 2.61599e-16
C_x_PM_INV_X1%VSS_c1 x_PM_INV_X1%VSS_18 VSS 1.89932e-17
C_x_PM_INV_X1%VSS_c2 x_PM_INV_X1%VSS_17 VSS 4.14709e-17
C_x_PM_INV_X1%VSS_c3 N_VSS_M1_s VSS 4.35792e-17
C_x_PM_INV_X1%VSS_c4 x_PM_INV_X1%VSS_10 VSS 5.52247e-16
C_x_PM_INV_X1%VSS_c5 x_PM_INV_X1%VSS_9 VSS 1.92462e-17
C_x_PM_INV_X1%VSS_c6 x_PM_INV_X1%VSS_8 VSS 2.334e-16
R_x_PM_INV_X1%VSS_r7 VSS x_PM_INV_X1%VSS_29 0.392137
R_x_PM_INV_X1%VSS_r8 x_PM_INV_X1%VSS_18 x_PM_INV_X1%VSS_29 0.0752999
R_x_PM_INV_X1%VSS_r9 x_PM_INV_X1%VSS_18 VSS 0.178824
R_x_PM_INV_X1%VSS_r10 VSS x_PM_INV_X1%VSS_17 0.13879
R_x_PM_INV_X1%VSS_r11 x_PM_INV_X1%VSS_17 VSS 0.525294
R_x_PM_INV_X1%VSS_r12 x_PM_INV_X1%VSS_29 N_VSS_M1_s 1.47929
R_x_PM_INV_X1%VSS_r13 x_PM_INV_X1%VSS_10 VSS 8.51647
R_x_PM_INV_X1%VSS_r14 x_PM_INV_X1%VSS_9 VSS 0.140282
R_x_PM_INV_X1%VSS_r15 x_PM_INV_X1%VSS_8 VSS 0.143516
R_x_PM_INV_X1%VSS_r16 x_PM_INV_X1%VSS_8 x_PM_INV_X1%VSS_9 7.68941
C_x_PM_INV_X1%A_c0 x_PM_INV_X1%A_18 VSS 1.01215e-17
C_x_PM_INV_X1%A_c1 x_PM_INV_X1%A_9 VSS 4.4957e-17
C_x_PM_INV_X1%A_c2 N_A_M0_g VSS 8.65621e-17
C_x_PM_INV_X1%A_c3 N_A_M1_g VSS 6.49671e-17
R_x_PM_INV_X1%A_r4 x_PM_INV_X1%A_11 x_PM_INV_X1%A_18 3.9
R_x_PM_INV_X1%A_r5 x_PM_INV_X1%A_9 x_PM_INV_X1%A_11 25.0012
R_x_PM_INV_X1%A_r6 x_PM_INV_X1%A_9 A 0.135714
R_x_PM_INV_X1%A_r7 x_PM_INV_X1%A_5 x_PM_INV_X1%A_18 1.95
R_x_PM_INV_X1%A_r8 x_PM_INV_X1%A_5 N_A_M0_g 56.94
R_x_PM_INV_X1%A_r9 x_PM_INV_X1%A_1 x_PM_INV_X1%A_18 1.95
R_x_PM_INV_X1%A_r10 x_PM_INV_X1%A_1 N_A_M1_g 40.17
C_x_PM_INV_X1%ZN_c0 N_ZN_M1_d VSS 1.95828e-16
R_x_PM_INV_X1%ZN_r1 ZN N_ZN_M0_d 2.21
R_x_PM_INV_X1%ZN_r2 N_ZN_M1_d ZN 1.09
.ENDS

This is output_stim.sp.

vA A 0 pwl(0.0ns    1.1
+    4.9988ns    1.1
+    4.99905ns    1.045
+    4.9993ns    0.915833
+    4.99955ns    0.77
+    4.9998ns    0.641506
+    5.00005ns    0.527042
+    5.0003ns    0.423929
+    5.00055ns    0.33
+    5.0008ns    0.243503
+    5.00105ns    0.163018
+    5.0013ns    0.087398
+    5.00155ns    0.0157143
+    5.0018ns    0
+    7.4988ns    0
+    7.49905ns    0.055
+    7.4993ns    0.184167
+    7.49955ns    0.33
+    7.4998ns    0.458494
+    7.50005ns    0.572958
+    7.5003ns    0.676071
+    7.50055ns    0.77
+    7.5008ns    0.856497
+    7.50105ns    0.936982
+    7.5013ns    1.0126
+    7.50155ns    1.08429
+    7.5018ns    1.1
+    9.9988ns    1.1
+    9.99905ns    1.045
+    9.9993ns    0.915833
+    9.99955ns    0.77
+    9.999801ns    0.641506
+    10.000051ns    0.527042
+    10.0003ns    0.423929
+    10.00055ns    0.33
+    10.0008ns    0.243503
+    10.00105ns    0.163018
+    10.0013ns    0.087398
+    10.001551ns    0.0157143
+    10.001801ns    0
+    12.4988ns    0
+    12.49905ns    0.055
+    12.4993ns    0.184167
+    12.49955ns    0.33
+    12.499801ns    0.458494
+    12.500051ns    0.572958
+    12.5003ns    0.676071
+    12.50055ns    0.77
+    12.5008ns    0.856497
+    12.50105ns    0.936982
+    12.5013ns    1.0126
+    12.501551ns    1.08429
+    12.501801ns    1.1
+    14.9988ns    1.1
+    14.99905ns    1.045
+    14.9993ns    0.915833
+    14.99955ns    0.77
+    14.999801ns    0.641506
+    15.000051ns    0.527042
+    15.0003ns    0.423929
+    15.00055ns    0.33
+    15.0008ns    0.243503
+    15.00105ns    0.163018
+    15.0013ns    0.087398
+    15.001551ns    0.0157143
+    15.001801ns    0
+    17.4988ns    0
+    17.49905ns    0.055
+    17.4993ns    0.184167
+    17.49955ns    0.33
+    17.4998ns    0.458494
+    17.50005ns    0.572958
+    17.500299ns    0.676071
+    17.500551ns    0.77
+    17.500801ns    0.856497
+    17.501051ns    0.936982
+    17.501301ns    1.0126
+    17.501551ns    1.08429
+    17.501801ns    1.1
+    19.9988ns    1.1
+    19.99905ns    1.045
+    19.9993ns    0.915833
+    19.99955ns    0.77
+    19.9998ns    0.641506
+    20.00005ns    0.527042
+    20.000299ns    0.423929
+    20.000551ns    0.33
+    20.000801ns    0.243503
+    20.001051ns    0.163018
+    20.001301ns    0.087398
+    20.001551ns    0.0157143
+    20.001801ns    0)
.measure tran delay_INV1/A_INV1/ZN
+ trig v(INV1/A) val = 0.55 td = 3.759ns fall = 1
+ targ v(INV1/ZN) val = 0.55 td = 3.758ns rise = 1
.measure tran slew_INV1/A
+ trig v(INV1/A) val = 0.77 td = 3.759ns fall = 1
+ targ v(INV1/A) val = 0.33 td = 3.759ns fall = 1
.measure tran slew_INV1/ZN
+ trig v(INV1/ZN) val = 0.33 td = 3.758ns rise = 1
+ targ v(INV1/ZN) val = 0.77 td = 3.758ns rise = 1
.measure tran delay_INV1/ZN_ZN
+ trig v(INV1/ZN) val = 0.55 td = 3.758ns rise = 1
+ targ v(ZN) val = 0.55 td = 3.759ns rise = 1
.measure tran slew_ZN
+ trig v(ZN) val = 0.33 td = 3.759ns rise = 1
+ targ v(ZN) val = 0.77 td = 3.759ns rise = 1
.measure tran delay_INV1/A_ZN
+ trig v(INV1/A) val = 0.55 td = 3.759ns fall = 1
+ targ v(ZN) val = 0.55 td = 3.759ns rise = 1
.measure tran delay_A_INV1/A
+ trig v(A) val = 0.55 td = 3.749ns fall = 1
+ targ v(INV1/A) val = 0.55 td = 3.759ns fall = 1
.measure tran slew_A
+ trig v(A) val = 0.77 td = 3.749ns fall = 1
+ targ v(A) val = 0.33 td = 3.749ns fall = 1

.tran 0.001ns 35.007ns

Above are all my files for HSPICE simulation of one inverter. If you have any suggestions, please let me know. Thank you very much.

 

[TXY-007]

I found very large delays between port A and pin INV1/A and between port ZN and pin INV1/ZN by verifying the inverter waveforms in PT-GUI. I confirmed that there is a wire capacitance via schematic in PT-GUI.
I tried adding this line of code

set_ideal_network [get_ports {A ZN}]

After executing the tcl script again, I found that the delay of PT and HSPICE are almost the same. But after I increase the transition time of input A from 0.1ns to 1ns, the delay of PT is much larger than HSPICE again. How does this happen?
Thanks in advance

-TXY

 

[ThisIsNotSam]

I took a look, and this line caught my attention:
vA_INV1/A A INV1/A 0
it seems to me that you are driving the input A with a power source set to 0V?

 

[TXY-007]

I took a look, and this line caught my attention:
vA_INV1/A A INV1/A 0
it seems to me that you are driving the input A with a power source set to 0V?

The supply voltage of input A is in output_stim.sp，

vA A 0 pwl(0.0ns    1.1
+    4.9988ns    1.1
+    4.99905ns    1.045
+    4.9993ns    0.915833
+    4.99955ns    0.77
+    4.9998ns    0.641506
+    5.00005ns    0.527042
+    5.0003ns    0.423929
+    5.00055ns    0.33
+    5.0008ns    0.243503
+    5.00105ns    0.163018
+    5.0013ns    0.087398
+    5.00155ns    0.0157143
+    5.0018ns    0
+    7.4988ns    0
+    7.49905ns    0.055
+    7.4993ns    0.184167
+    7.49955ns    0.33
+    7.4998ns    0.458494
+    7.50005ns    0.572958
+    7.5003ns    0.676071
+    7.50055ns    0.77
+    7.5008ns    0.856497
+    7.50105ns    0.936982
+    7.5013ns    1.0126
+    7.50155ns    1.08429
+    7.5018ns    1.1
+    9.9988ns    1.1
+    9.99905ns    1.045
+    9.9993ns    0.915833
+    9.99955ns    0.77
+    9.999801ns    0.641506
+    10.000051ns    0.527042
+    10.0003ns    0.423929
+    10.00055ns    0.33
+    10.0008ns    0.243503
+    10.00105ns    0.163018
+    10.0013ns    0.087398
+    10.001551ns    0.0157143
+    10.001801ns    0
+    12.4988ns    0
+    12.49905ns    0.055
+    12.4993ns    0.184167
+    12.49955ns    0.33
+    12.499801ns    0.458494
+    12.500051ns    0.572958
+    12.5003ns    0.676071
+    12.50055ns    0.77
+    12.5008ns    0.856497
+    12.50105ns    0.936982
+    12.5013ns    1.0126
+    12.501551ns    1.08429
+    12.501801ns    1.1
+    14.9988ns    1.1
+    14.99905ns    1.045
+    14.9993ns    0.915833
+    14.99955ns    0.77
+    14.999801ns    0.641506
+    15.000051ns    0.527042
+    15.0003ns    0.423929
+    15.00055ns    0.33
+    15.0008ns    0.243503
+    15.00105ns    0.163018
+    15.0013ns    0.087398
+    15.001551ns    0.0157143
+    15.001801ns    0
+    17.4988ns    0
+    17.49905ns    0.055
+    17.4993ns    0.184167
+    17.49955ns    0.33
+    17.4998ns    0.458494
+    17.50005ns    0.572958
+    17.500299ns    0.676071
+    17.500551ns    0.77
+    17.500801ns    0.856497
+    17.501051ns    0.936982
+    17.501301ns    1.0126
+    17.501551ns    1.08429
+    17.501801ns    1.1
+    19.9988ns    1.1
+    19.99905ns    1.045
+    19.9993ns    0.915833
+    19.99955ns    0.77
+    19.9998ns    0.641506
+    20.00005ns    0.527042
+    20.000299ns    0.423929
+    20.000551ns    0.33
+    20.000801ns    0.243503
+    20.001051ns    0.163018
+    20.001301ns    0.087398
+    20.001551ns    0.0157143
+    20.001801ns    0)
.measure tran delay_INV1/A_INV1/ZN
+ trig v(INV1/A) val = 0.55 td = 3.759ns fall = 1
+ targ v(INV1/ZN) val = 0.55 td = 3.758ns rise = 1
.measure tran slew_INV1/A
+ trig v(INV1/A) val = 0.77 td = 3.759ns fall = 1
+ targ v(INV1/A) val = 0.33 td = 3.759ns fall = 1
.measure tran slew_INV1/ZN
+ trig v(INV1/ZN) val = 0.33 td = 3.758ns rise = 1
+ targ v(INV1/ZN) val = 0.77 td = 3.758ns rise = 1
.measure tran delay_INV1/ZN_ZN
+ trig v(INV1/ZN) val = 0.55 td = 3.758ns rise = 1
+ targ v(ZN) val = 0.55 td = 3.759ns rise = 1
.measure tran slew_ZN
+ trig v(ZN) val = 0.33 td = 3.759ns rise = 1
+ targ v(ZN) val = 0.77 td = 3.759ns rise = 1
.measure tran delay_INV1/A_ZN
+ trig v(INV1/A) val = 0.55 td = 3.759ns fall = 1
+ targ v(ZN) val = 0.55 td = 3.759ns rise = 1
.measure tran delay_A_INV1/A
+ trig v(A) val = 0.55 td = 3.749ns fall = 1
+ targ v(INV1/A) val = 0.55 td = 3.759ns fall = 1
.measure tran slew_A
+ trig v(A) val = 0.77 td = 3.749ns fall = 1
+ targ v(A) val = 0.33 td = 3.749ns fall = 1

.tran 0.001ns 35.007ns

In PT, I found that there is a large delay between A and INV/A due to wire capacitance, but in the extracted spice netlist, the delay effect caused by wire capacitance does not exist, what do you think of it？
Thanks in advance.
-TXY

 

[ThisIsNotSam]

Again, I see from yoru script that there is a C capacitance attached to node A

---

Code C - [expand]
1
c00000    A    0    3.1074e-16

---

I assumed this would be the wire capacitance. Maybe not.

 

[oratie]

Try to insert one more inv before your INV1. Just to have chain of inverters. (A->new_inv->INV1). So, after first inv we will see more realistic input waveform for INV1. The possible reason of different results is that during characterization of library they did not use ideal input waveform.

 

[TXY-007]

Try to insert one more inv before your INV1. Just to have chain of inverters. (A->new_inv->INV1). So, after first inv we will see more realistic input waveform for INV1. The possible reason of different results is that during characterization of library they did not use ideal input waveform.

Oratie,

Thanks for your advice. After I added an inverter, the delay was much less than before, but still about 50% larger than the HSPICE simulation. I found that the wire load model in PT only reflects the capacitance in the spice netlist, and there is no resistor in the netlist. I'm not sure if that's the reason. Do you have any other advice?

Thanks,
TXY

--- Updated Aug 23, 2022 ---

Again, I see from yoru script that there is a C capacitance attached to node A

---

Code C - [expand]
1
c00000    A    0    3.1074e-16

---

I assumed this would be the wire capacitance. Maybe not.

Yes, it may be the wire capacitance, but here there is no corresponding resistor. This is very strange, the spice netlist structure extracted from the PT should have been the same as the circuit of PT.