extra port in calibre LVS

[deepak242003]

instances non-floating extra pins

Hello all,

i am getting this error :

INSTANCES OF CELLS WITH NON-FLOATING EXTRA PINS......

although there is no extra labels in the layout...... anybody found such error???


Deepak.

 

[cop02ia]

: in calibre lvs

Hi,

I'm not sure of the exact problem with the limited info. here, but could I suggest something:
Have you considered Calibre not detecting labels as ports?
How does Calibre define a port in your LVS check? Does it check for label types or other layer types?

The reason I'm asking is that in some LVS checks (well, most that I've seen anyway), a port is detected according to certain layers. The labels just tell us what the port name is (instead of letting the physical verification tool auto-name it).

Some designed cells have ports only at specific places, e.g. a square-chaped port on the centre-left & centre-right of the cell (although physical connection can join from above the cell & right at the middle) while the rest of the cell is regarded as "Don't Touch" with blockages - this is to make the routing more uniform/clean. So, as in this example, Calibre might see 2 ports although they are actually the same & connected within the cell.

A simple illustration is as below. Port for IN_A1 path is located at both ends of the cell as connection can come from both sides. Suppose metal1 (gds layer 6 datatype 0) is used for connection, the ports extracted (recognised) here are 2 squares on metal1_port (gds layer 6 datatype 4) at the 'X' location. The ports are connected together on metal1 internally while routing connects to only 1 port. Calibre might view the other port as unconnected.
_____________
|
X - - - - - - - - - X (IN_A1)
|____________|

 

[vikramc98406]

Hi cop02ia,

Although edaboard was not allowing to reply , I would like to say thanks to you.
I have faced this issue and was helpful with your update to fix my issue.

Not sure why designers (in my case std-cell designers) will do this.

Thanks

 

[erikl]

Not sure why designers (in my case std-cell designers) will do this.

Because of the capability to connect from either side, I guess.