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thank you very much
i can use dc synthesize the project and produce synthesized netlist in verilog format ,but after I imported the netlist into cadence and use nc-verilog to perform post-simulation,i met software error ,maybe caused by cadence software bug .i can not deal with it .
so i want generate edif file and import it .
i tried using CSI to call DC to perform synthesis and then import design .but i found it can not generate edif file at all.maybe it caused by mismatch of symbol scales.